Aaron Durbin 3d69cce280 UPSTREAM: x86: provide stage_exit() like arm ... The arm architectures have a stage_exit() function which takes a void * pointer as an entry point. Provide the same API for x86. This can make the booting paths less architecture-specific. BUG=chrome-os-partner:30784 TEST=built for nyan. Change-Id: I4ecfbf32f38f2e3817381b63e1f97e92654c5f97 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5086 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: https://chromium-review.googlesource.com/209591 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org>		2014-07-28 19:19:16 +00:00
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arch	UPSTREAM: x86: provide stage_exit() like arm	2014-07-28 19:19:16 +00:00
console	vboot2: implement select_firmware for pre-romstage verification	2014-06-30 18:45:09 +00:00
cpu	x86: Initialize drivers in SMM context if needed	2014-06-20 18:27:33 +00:00
device	i2c: Add software_i2c driver for I2C debugging and emulation	2014-05-19 20:34:31 +00:00
drivers	vboot2: read secdata and nvdata	2014-07-23 02:29:18 +00:00
ec	vboot2: read dev and recovery switch	2014-07-02 00:45:22 +00:00
include	Use a common boardid.h instead of per board copies	2014-07-25 03:45:43 +00:00
lib	rmodule: Correct the typecast with proper parenthesis	2014-07-23 23:14:18 +00:00
mainboard	Use a common boardid.h instead of per board copies	2014-07-25 03:45:43 +00:00
northbridge	coreboot: Rename coreboot_ram stage to ramstage	2014-05-07 23:30:23 +00:00
soc	t132: Get rid of Kconfig warning	2014-07-23 23:14:22 +00:00
southbridge	coreboot: Rename coreboot_ram stage to ramstage	2014-05-07 23:30:23 +00:00
superio	pnp: Allow setting of misc register 0xf4 in device tree	2013-12-20 00:37:38 +00:00
vendorcode	UPSTREAM: x86: provide stage_exit() like arm	2014-07-28 19:19:16 +00:00
Kconfig	coreboot arm64: Add support for arm64 into coreboot framework	2014-05-15 23:52:58 +00:00