coreboot/src/soc
David Hendricks 2928922336 tegra124: implement x2 mode for SPI transfers on CBFS media
This implements x2 mode when reading CBFS media over SPI.

In theory this effectively doubles our throughput, though the initial
results were almost negligibly better. Using a logic analyzer we see
a pattern of 12 clocks, ~70ns delay, 4 clocks, ~310ns delay. So if we
want to see further gains here then we'll probably need to tune AHB
arbitration and utilization to eliminate bubbles/stalls when copying
from APB DMA.

BUG=none
BRANCH=none
TEST=built and booted on Nyan.
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I33d6ae30923fc42b4dc7103d029085985472cf3e
Reviewed-on: https://chromium-review.googlesource.com/177835
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
2013-12-17 08:00:10 +00:00
..
intel baytrail: Expose IOSF as ACPI object 2013-12-14 02:31:42 +00:00
nvidia tegra124: implement x2 mode for SPI transfers on CBFS media 2013-12-17 08:00:10 +00:00
samsung Add check_member macro to allow clean and easy struct offset checking 2013-12-11 22:12:25 +00:00
Kconfig ARM: Generalize armv7 as arm. 2013-10-02 09:18:44 +00:00
Makefile.inc armv7: Move Exynos from 'cpu' to 'soc'. 2013-10-01 08:16:46 +00:00