25084bd040
This patch overhauls the structure of the code that saves SDRAM parameters to PMC registers for LP0 support, which had formerly been very close to the U-Boot implementation. The new code keeps the "translation table" entries as they are, but redefines the macros to output hardcoded assignments instead of structure entries that need to be parsed at runtime. It explicitly allows the compiler to merge and reorder all accesses (under the assumption that PMC scratch registers are essentially "like memory", without read or write side effects), which generates much better and more importantly smaller code. BUG=chrome-os-partner:25062 TEST=Nyan_big boots (on my Norrin, with the required board_id hacks) and can suspend/resume fine to LP0. Measured (uncompressed) romstage size for nyan_big at 25K without LP0 support, 43K with the old U-Boot style implementation and 32K with this patch. Execution time of the function drops from 1.2ms to .09ms. Change-Id: Id52577c14d22ee67f167f10c3b976a037b1a321f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/184388 |
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