coreboot/src
Tony Huang 23f5df6eae mb/google/nissa/var/yavilla: Add H58G66CK8BX147 to RAM ID table
DRAM Part Name                 ID to assign
H58G66CK8BX147                 1 (0001)

Yavilla use three memory strap pins for RAM_ID definition and it's consumed.
Since the MT62F1G32D4DR-031 WT:B was never used so it's safe to remove.
This CL make the H58G66CK8BX147 to set for RAM_ID1.

BUG=b:425545256
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I9df2710ceb77e4ace6de8976adc1285ef9784c03
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88121
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-06-23 02:11:53 +00:00
..
acpi Revert "acpi,Makefile: Add preload_acpi_dsdt" 2025-04-14 13:55:42 +00:00
arch arch/x86: Unify GDT entries 2025-05-08 12:29:24 +00:00
commonlib treewide: Work around GCC 15 Werror=unterminated-string-initialization 2025-06-09 07:19:09 +00:00
console console/i2c_smbus: Allow to send data w/o register offset 2024-07-11 00:06:22 +00:00
cpu cpu/intel/haswell: Export PCODE mailbox functions 2025-05-27 15:07:25 +00:00
device device/device_util.c: Complete function documentation 2025-06-15 12:55:59 +00:00
drivers drivers/intel: Refactor logo rendering with helper functions 2025-06-23 02:05:23 +00:00
ec mb/google/brox: Enable support for Realtek EC 2025-06-20 17:48:07 +00:00
include {lib, drivers/intel}: Add splash screen footer 2025-06-23 02:04:26 +00:00
lib {lib, drivers/intel}: Add splash screen footer 2025-06-23 02:04:26 +00:00
mainboard mb/google/nissa/var/yavilla: Add H58G66CK8BX147 to RAM ID table 2025-06-23 02:11:53 +00:00
northbridge Haswell NRI: Measure per-task execution time 2025-06-11 13:25:59 +00:00
sbom src, util: Clean up makefile.inc in text, help & comments 2024-01-26 20:15:18 +00:00
security security/vboot: Back up CMOS data later boot phase 2025-06-05 13:36:19 +00:00
soc soc/qc/x1p42100: Allow building QC platform without upstream blobs 2025-06-23 02:06:14 +00:00
southbridge sb/intel/lynxpoint: Add CFR objects for existing options 2025-04-25 14:24:47 +00:00
superio src/superio/nuvoton: Add HWM initialization code 2025-06-11 13:31:25 +00:00
vendorcode vc/google/chromeos: Don't pack cb_plus_logo.bmp if footer is present 2025-06-23 02:05:15 +00:00
Kconfig security/vboot: Back up CMOS data later boot phase 2025-06-05 13:36:19 +00:00