coreboot/src/soc
Duncan Laurie 1b520b577f baytrail: Set PMC PTPS register correctly
I messed up in setting this register, it should be using Tj_max-Temp
which in the default case works out to be 90-90=0.

This was apparently heavly throttling the CPU at idle temps.

BUG=chrome-os-partner:17279
BRANCH=baytrail
TEST=build and boot on rambi, run graphics_WebGLPerformance test

Change-Id: I4338280cf50db84dc44313d6fb6771ea5af21dad
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183280
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
2014-01-21 01:13:11 +00:00
..
intel baytrail: Set PMC PTPS register correctly 2014-01-21 01:13:11 +00:00
nvidia arm: Thumb ALL the things! 2014-01-14 03:29:48 +00:00
samsung Add check_member macro to allow clean and easy struct offset checking 2013-12-11 22:12:25 +00:00
Kconfig ARM: Generalize armv7 as arm. 2013-10-02 09:18:44 +00:00
Makefile.inc armv7: Move Exynos from 'cpu' to 'soc'. 2013-10-01 08:16:46 +00:00