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Paul Ma 0f3c9e9db6 Jerry: add SAMSUNG K4B4G1646Q-HYK0 ddr3 sdram support
K4B4G1646Q-HYK0 is different form K4B4G1646D-BYK0 with chip physical
package and they have the same config parameters.

BRANCH=none
BUG=chrome-os-partner:34940
TEST=boot on Jerry board with K4B4G1646Q-HYK0

Change-Id: I31bcb348a45ff76e8e08127063bd0d04443ccb79
Signed-off-by: Paul Ma <magf@bitland.com.cn>
Reviewed-on: https://chromium-review.googlesource.com/241787
Reviewed-by: Julius Werner <jwerner@chromium.org>
Trybot-Ready: Julius Werner <jwerner@chromium.org>
(cherry picked from commit e925d784e1ebe444f5a5bcab47c8a661b0c6c527)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/243096
2015-01-24 02:13:27 +00:00
configs Brain: Initial import. 2015-01-21 01:16:33 +00:00
documentation documentation: Add documentation for timestamp library 2014-11-14 23:57:04 +00:00
payloads usb: dwc2: using a new FIFO allocation method 2015-01-21 01:17:25 +00:00
src Jerry: add SAMSUNG K4B4G1646Q-HYK0 ddr3 sdram support 2015-01-24 02:13:27 +00:00
util timestamps: You can never have enough of them! 2014-12-10 02:00:24 +00:00
.gitignore rmodules: add support for rmodtool 2014-03-31 22:25:57 +00:00
COMMIT-QUEUE.ini COMMIT-QUEUE.ini: Add documentation. 2013-11-01 14:08:42 +00:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
Makefile Makefile: Fix dependency tracking for ramstage objects 2014-12-06 01:10:41 +00:00
Makefile.inc Makefile: Fix dependency tracking for ramstage objects 2014-12-06 01:10:41 +00:00
PRESUBMIT.cfg chromeos: Add PRESUBMIT.cfg 2013-05-01 14:31:10 -07:00
README Update README with newer version of the text from the web page 2011-06-15 10:16:33 +02:00
toolchain.inc ARM: Remove -mno-unaligned-access 2015-01-21 01:17:51 +00:00

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * gcc / g++
 * make

Optional:

 * doxygen (for generating/viewing documentation)
 * iasl (for targets with ACPI support)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.