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usb: dwc2: using a new FIFO allocation method

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Total FIFO length is split into many 512 byte blocks,
because the max packet size in coreboot is 512 byte,
then allot these blocks to GRXFSIZ and GNPTXFSZ evenly.
This method avoids the hardcoding and make the FIFO size
value work for dwc2 controller that has different FIFO ram size.

BUG=chrome-os-partner:32634
BRANCH=None
TEST=Boot kernel from USB

Change-Id: Ib50a08c193f7f65392810ca3528a97554f2c3999
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/233119
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/242156
Tested-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Julius Werner <jwerner@chromium.org>
This commit is contained in:
huang lin 2014-12-04 18:25:47 +08:00 • committed by ChromeOS Commit Bot
commit ca358e2acc
2 changed files with 33 additions and 6 deletions
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23
payloads/libpayload/drivers/usb/dwc2.c
View file

@ -35,11 +35,12 @@ static void dwc2_reinit(hci_t *controller)
gintsts_t gintsts = { .d32 = 0 };
gahbcfg_t gahbcfg = { .d32 = 0 };
grxfsiz_t grxfsiz = { .d32 = 0 };
ghwcfg3_t hwcfg3 = { .d32 = 0 };
hcintmsk_t hcintmsk = { .d32 = 0 };
gnptxfsiz_t gnptxfsiz = { .d32 = 0 };
const int timeout = 10000;
int i;
int i, fifo_blocks, tx_blocks;
/* Wait for AHB idle */
for (i = 0; i < timeout; i++) {
@ -86,10 +87,24 @@ static void dwc2_reinit(hci_t *controller)
* The non-periodic tx fifo and rx fifo share one continuous
* piece of IP-internal SRAM.
*/
grxfsiz.rxfdep = DWC2_RXFIFO_DEPTH;
/*
* Read total data FIFO depth from HWCFG3
* this value is in terms of 32-bit words
*/
hwcfg3.d32 = readl(&reg->core.ghwcfg3);
/*
* Reserve 2 spaces for the status entries of receive packets
* and 2 spaces for bulk an control OUT endpoints. Calculate how
* many blocks can be alloted, assume largest packet size is 512.
*/
fifo_blocks = (hwcfg3.dfifodepth - 4) / (512 / 4);
tx_blocks = fifo_blocks / 2;
grxfsiz.rxfdep = (fifo_blocks - tx_blocks) * (512 / 4) + 4;
writel(grxfsiz.d32, &reg->core.grxfsiz);
gnptxfsiz.nptxfstaddr = DWC2_RXFIFO_DEPTH;
gnptxfsiz.nptxfdep = DWC2_NPTXFIFO_DEPTH;
gnptxfsiz.nptxfstaddr = grxfsiz.rxfdep;
gnptxfsiz.nptxfdep = tx_blocks * (512 / 4);
writel(gnptxfsiz.d32, &reg->core.gnptxfsiz);
/* Init host channels */

16
payloads/libpayload/drivers/usb/dwc2_private.h
View file

@ -374,7 +374,6 @@ typedef union {
struct {
unsigned nptxfstaddr:16;
unsigned nptxfdep:16;
#define DWC2_NPTXFIFO_DEPTH 0x80
};
} gnptxfsiz_t;
@ -390,7 +389,6 @@ typedef union {
*/
struct {
unsigned rxfdep:16;
#define DWC2_RXFIFO_DEPTH 0x200
unsigned reserved:16;
};
} grxfsiz_t;
@ -437,6 +435,20 @@ typedef union {
};
} gintsts_t;
/**
* This union represents the bit fields of the User HW Config3 Register
* (GHWCFG3).
*/
typedef union {
/* raw register data */
uint32_t d32;
/* register bits */
struct {
unsigned reserved:16;
unsigned dfifodepth:16;
};
} ghwcfg3_t;
/**
* This union represents the bit fields in the Host Configuration Register.
*/