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2 commits

Author SHA1 Message Date
Patrick Rudolph
ad342a4589 nb/intel/sandybridge: Fix PEG disablement
Fix regression introduced by:
3660c0fc65
"northbridge/intel/sandybridge: Enable PEG clock-gating on demand"

Issue observed:
GNU/Linux kernel crashes in earlyinit on systems without PEG devices.
The crash occurs on every boot in different functions.
There's no problem on systems with PEG enabled.

Test system:
 * Lenovo T530
 * Intel Core i5-3320M CPU
 * Fedora GNU/Linux 4.1
 * PEG disabled in devicetree

Problem description:
Tests shows that modifing PEG chicken bit or device enable bits
after setting BIOS_RESET_CPL causes random crashes in GNU/Linux.

Problem solution:
Disable PEG devices before setting BIOS_RESET_CPL.

Final testing results:
No more random kernel crashes.

Change-Id: I4a967c2d00d7d1e4426cf5abdd5f616c21557da7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/12112
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
(cherry picked from commit aad34cda4b)
Reviewed-on: https://review.coreboot.org/12456
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-14 21:20:20 +01:00
Nico Huber
ca374d34ed sandybridge: Disable parallel CPU initialization
Disable the parallel CPU initialization for model_206ax, that is Sandy
Bridge and Ivy Bridge processors. We never did it the way that Intel
recommends and it became unreliable with the introduction of SMM_MODULES
in commit a3e41c0 Migrate 206ax to SMM_MODULES.

Tested by booting kontron/ktqm77 2.6k times into Linux user space. No
issues so far.

Change-Id: Idffc352341419f22a36bf772534a5e11e711edf1
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12329
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-16 17:57:43 +01:00
2 changed files with 5 additions and 4 deletions

View file

@ -17,7 +17,6 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_LAPIC
select SMM_TSEG
select SUPPORT_CPU_UCODE_IN_CBFS
select PARALLEL_CPU_INIT
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select LAPIC_MONOTONIC_TIMER

View file

@ -431,6 +431,11 @@ static void northbridge_init(struct device *dev)
}
MCHBAR32(0x5f10) = bridge_type;
/* Turn off unused devices. Has to be done before
* setting BIOS_RESET_CPL.
*/
disable_peg();
/*
* Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
* that BIOS has initialized memory and power management
@ -456,9 +461,6 @@ static void northbridge_init(struct device *dev)
/* Set here before graphics PM init */
MCHBAR32(0x5500) = 0x00100001;
/* Turn off unused devices */
disable_peg();
}
static void northbridge_enable(device_t dev)