Due to some LVDS cable constraints even and odd lanes needs
to be swapped on certain hardware. The hardware ID will be used to
distinguish between these two cases. The swapping itself will be done by
PTN3460, which is configurable for that.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/17576
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Change-Id: I339b2321a8ed1bc3bbf10aa8e50eb598b14b15fa
Reviewed-on: https://chromium-review.googlesource.com/415077
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the location of HWID field so that hwilib supports this
value as well.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/17575
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Change-Id: If6d4695f861232231ac8f9c247c0a10410dac1c5
Reviewed-on: https://chromium-review.googlesource.com/415076
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Resetting a Realtek 8168 NIC only makes sense on targets that have
such a device.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17577
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: I8ac9e8da1d8ecaacb19b4610a9b75f107915d691
Reviewed-on: https://chromium-review.googlesource.com/415075
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Asserts are only fatal if CONFIG_FATAL_ASSERTS is enabled in Kconfig.
By default this is disabled, so the assert is generally just a printf.
Die if someone decides to pass in an invalid bus number for some reason.
Addresses coverity issue 1349858 - Out-of-bounds read
Signed-off-by: Martin Roth <martinroth@google.com>
BUG=None
BRANCH=None
TEST=None
Reviewed-on: https://review.coreboot.org/17484
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: I9d79bc336cbbfde31f655cfd271f101e7a90ab1b
Reviewed-on: https://chromium-review.googlesource.com/415068
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If smbus_read_byte returned an error when reading the DIMM size,
this value would be used as an offset into an array.
Check for the error, and set the DIMM size to 0 if there's
a problem.
Addresses coverity issue 1229658 - Negative array index read
Signed-off-by: Martin Roth <martinroth@google.com>
BUG=None
BRANCH=None
TEST=None
Reviewed-on: https://review.coreboot.org/17485
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: I6461a0fae819dd9261adbb411c4bba07520d076d
Reviewed-on: https://chromium-review.googlesource.com/415067
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The lb_serial structure had some new entries added, which were not being
filled in.
Fill in the values so they're not undefined.
Addresses coverity error 1354778 - Uninitialized scalar variable
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17482
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: Ia7ce07f6e4e058c91c2e063f3225497271ef93ff
Reviewed-on: https://chromium-review.googlesource.com/415066
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The lb_serial structure had some new entries added, which were not being
filled in.
Fill in the values so they're not undefined.
Addresses coverity error 1354778 - Uninitialized scalar variable
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17483
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: I57f024c35f79397d0e9fd0c800b1b0f4075caac1
Reviewed-on: https://chromium-review.googlesource.com/415065
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When IDSOPT_TRACING_ENABLED is TRUE build fails with
"cast from pointer to integer of different size"
Use "UINTN" as is done in Family 16h.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: ukasz Dobrowolski <lukasz@dobrowolski.io>
Reviewed-on: https://review.coreboot.org/17406
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: I362e67fc83aa609155f959535f33be9c150c7636
Reviewed-on: https://chromium-review.googlesource.com/415058
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
FPR is an attribute of the SPI flash component and not of the SPI bus
itself. Rename functions, file names and Kconfig option to make sure
this is conveyed correctly.
BUG=None
BRANCH=None
TEST=Compiles successfully.
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17560
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I9f06f1a8ee28b8c56db64ddd6a19dd9179c54f50
Reviewed-on: https://chromium-review.googlesource.com/415057
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
flash_programmer_probe is a property of the spi flash driver and does
not belong in the spi_slave structure. Thus, make
spi_flash_programmer_probe a callback from the spi_flash_probe
function. Logic still remains the same as before (order matters):
1. Try spi_flash_programmer_probe without force option
2. Try generic flash probing
3. Try spi_flash_programmer_probe with force option
If none of the above steps work, fail probing. Flash controller is
expected to honor force option to decide whether to perform specialized
probing or to defer to generic probing.
BUG=None
BRANCH=None
TEST=Compiles successfully
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17465
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I4163593eea034fa044ec2216e56d0ea3fbc86c7d
Reviewed-on: https://chromium-review.googlesource.com/415056
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
max_transfer_size is a property of the SPI controller and not of the spi
slave. Also, this is used only on one SoC currently. There is no need to
handle this at the spi flash layer.
This change moves the handling of max_transfer_size to SoC SPI driver
and gets rid of the max_transfer_size parameter.
BUG=None
BRANCH=None
TEST=Compiles successfully.
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17463
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Change-Id: I19a1d0a83395a58c2bc1614b24518a3220945a60
Reviewed-on: https://chromium-review.googlesource.com/415055
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
RW flag was added to spi_slave structure to get around a requirement on
some AMD flash controllers that need to group together all spi volatile
operations (write/erase). This rw flag is not a property or attribute of
the SPI slave or controller. Thus, instead of saving it in spi_slave
structure, clean up the SPI flash driver interface. This allows
chipsets/mainboards (that require volatile operations to be grouped) to
indicate beginning and end of such grouped operations.
New user APIs are added to allow users to perform probe, read, write,
erase, volatile group begin and end operations. Callbacks defined in
spi_flash structure are expected to be used only by the SPI flash
driver. Any chipset that requires grouping of volatile operations can
select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and
define callbacks for chipset_volatile_group_{begin,end}.
spi_claim_bus/spi_release_bus calls have been removed from the SPI flash
chip drivers which end up calling do_spi_flash_cmd since it already has
required calls for claiming and releasing SPI bus before performing a
read/write operation.
BUG=None
BRANCH=None
TEST=Compiles successfully.
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17462
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf
Reviewed-on: https://chromium-review.googlesource.com/415054
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds a copy of the Asus F2A85-M code with only minimal changes.
(to ensure that the code compiles)
A second commit will be published to remove the copied code parts that
don't apply to the MS-7221 and to make everything else actually work
on the MS-7221 board.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Renze Nicolai <renze@rnplus.nl>
Reviewed-on: https://review.coreboot.org/17494
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Change-Id: I1426c0876c7bfeb264231c0d338301133c721484
Reviewed-on: https://chromium-review.googlesource.com/415052
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This motherboard support Intel core 2 quads.
Before this change SeaBIOS was not usable, due to it crashing before it
got to load anything.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17537
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Change-Id: Ifdaaceace04f9ba0753aab2d3b05c0519367f91f
Reviewed-on: https://chromium-review.googlesource.com/415047
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If no maximum string length is specified, we're intentionally passing a
value of -1 to get the string length so that it's not limited. This
makes checking tools unhappy, so actively cast it to size_t before
passing it into strlen to show that it's not an accident.
Addresses coverity issue 1129133 - Argument cannot be negative
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17479
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: I40f8f2101e170a5c96fcd39c217aa414f4316473
Reviewed-on: https://chromium-review.googlesource.com/415044
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Stage cache will save ~20ms on S3 resume for apollolake platforms.
Implementing the cache in ramstage to save silicon init and reload
it on resume. This patch adds passing S3 status to silicon init in
order to verify that the wake is from S3 and not for some other
reason. This patch also includes changes needed for quark and
skylake platforms that require fsp 2.0.
BUG=chrome-os-partner:56941
BRANCH=none
TEST=built for reef and tested boot and S3 resume path saving 20ms
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/17460
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I99dc93c1d7a7d5cf8d8de1aa253a326ec67f05f6
Reviewed-on: https://chromium-review.googlesource.com/414562
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is a stopgap for when you use SUPERIO_SMSC_SMSCSUPERIO and the
interrupt is unmapped at reset, but for whatever reason the chip is
inaccessible in smscsuperio/superio.c::enable_dev() and thus the
devicetree.cb IRQ information is not applied in ramstage and then
serial console output fails to work for more than the UART FIFO depth
in the OS.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: https://review.coreboot.org/10807
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I00998088975569516f7caeb7f4098b48fe437889
Reviewed-on: https://chromium-review.googlesource.com/414558
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently, the coreboot log of a Lenovo X60, not having any IDE devices
connected, there is a trailing whitespace in the output.
[]
PCI: 00:1f.1 init ...
i82801gx_ide: initializing...
PCI: 00:1f.1 init finished in 11 usecs
[]
Reorder the whitespaces, so they are added when needed.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/11870
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I640e514c89fe0246a847d1fd088def1c88e864f8
Reviewed-on: https://chromium-review.googlesource.com/414557
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It's very dangerous to set bus master enable, and more so on
a NIC, where random broadcast packets can end up in memory
in unexpected ways.
If your kernel has trouble with the fact that we do not set
bus master enable, you need to fix your kernel.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17559
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Tested-by: build bot (Jenkins)
Change-Id: If07fde7961ad80125567240cb43db036346bef97
Reviewed-on: https://chromium-review.googlesource.com/414551
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When running with relocatable ramstage, the gdt loaded from c_start.S
is already in CBMEM (high memory). Thus, there's no need to create
a new copy of the gdt and reload.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17504
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I2750d30119fee01baf4748d8001a672d18a13fb0
Reviewed-on: https://chromium-review.googlesource.com/414550
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add bob in coreboot and update as necessary.
1. Add bob HWID
2. Add supported memory source
BUG=chrome-os-partner:59454
BRANCH=firmware-gru-8785.B
TEST=Build firmware passed
Change-Id: I0dcf47eb911337b176f73759a2c70a9dbf4dc68b
Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com>
Reviewed-on: https://chromium-review.googlesource.com/411083
Reviewed-by: Philip Chen <philipchen@chromium.org>
(cherry picked from commit c5925dfcf59ac755a26182744b2bde59e41a37cf)
Reviewed-on: https://chromium-review.googlesource.com/413744
Reviewed-by: Julius Werner <jwerner@chromium.org>
TRAINING, not TARINING.
BUG=none
BRANCH=none
TEST=still builds
Change-Id: I4940279ed7217cc20fe29c8b3603d1853acbfc5e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/411801
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
