This patch provides an option for CPU programming where coreboot
expected to load second microcode patch after BIOS Done bit is set
and before setting the BIOS Reset CPL bit.
BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I426b38cb1200e60398bc89515838e49ce0a98f06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64836
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Kconfig option `SOC_INTEL_ALDERLAKE_S3` which will adjust
the ACPI to not offer D3Cold when using S3.
This patch is the Alder Lake equivalent of CB:59024.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I04df8e106f9d53337b9eb5d2b9041b44a0e36684
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Support up to 10 PCIe source clock out, including source clock out 7, 8, 9.
This allows boards to use source clock 7, 8, 9.
BUG=b:233252409
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I0296974fb8557de1edea7f9ca2d96db0afd8a743
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63943
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
1. add timeout for root port detection and pass to FSP.
2. add 'slot implemented' flag and pass to FSP.
3. PcieRpSlotImplemented needs to be set when the root port is set to
hotplug. There is an assertion in FSP checking this.
4. PcieRpSlotImplemented is updated only when it is built-in as it is
default to slot implemented in FSP.
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I13feb1d2d67eaba634a3e700685132fba39e1525
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch creates a helper function named `initialize_microcode()`
to load microcode and ease for all function to peform loading
microcode using this helper function.
BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7155fc2da7383629930ce147a90ac582782fa5ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
As per Intel Processor EDS, BIOS_DONE bit needs to be set on
all CPUs via MSR.
Also, implement a function to perform any SoC recommended CPU
programming prior to post CPUs init. At present calling
`cpu_soc_bios_done()` for all CPUs from `before_post_cpus_init()`.
Note: It is expected that `before_post_cpus_init()` will be
extended with other CPU programming recommendations in follow up
patches, for example: reload microcode patch etc.
BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8066cd724c9f15d259aeb23f3aa71a2d224d5340
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch implements heci_init() API that perform initialization of
all HECI devices as per MAX_HECI_DEVICES config.
BUG=none
TEST=Able to build and boot google/taeko with this change. No CSE
error observed with `heci_init()` called from romstage.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia25e18a20cc749fc7eee39b0b591d41540fc14c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch ensures the IP initialization being done as part of MTL
bootblock code is able to complete the bootblock phase without any
visible hang.
The re-ordering in the MTL bootblock SoC programming is required to
ensure the SA early initialization is taking place prior to
performing any PCI Read/Write operation (like P2SB bar enabling for
IOE die etc.).
Additionally, Fast SPI init takes place prior to enabling ROM caching
etc.
BUG=b:224325352
TEST= Able to build and start booting the MTL simics.
Without this change, the code execution is stuck as below:
[NOTE ] coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8)
[DEBUG] CPU: Intel(R) Core(TM) i7 CPU (server) @ 2.00GHz
[DEBUG] CPU: ID a06a0, MeteorLake A0, ucode: 80000018
[DEBUG] CPU: AES supported, TXT supported, VT supported
[DEBUG] MCH: device id 7d02 (rev 00) is MeteorLake P
[DEBUG] PCH: device id 7e01 (rev 00) is MeteorLake SOC
[DEBUG] IGD: device id ffff (rev ff) is Unknown
[INFO ] PMC: Using default GPE route.
[INFO ] VBNV: CMOS invalid, restoring from flash
[ERROR] init_vbnv: failed to locate NVRAM
[EMERG] Cannot locate primary CBFS
Able to detect the Flash and reading the SPI flash layout in proper
with this change as below:
[NOTE ] coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8)
[DEBUG] CPU: Intel(R) Core(TM) i7 CPU (server) @ 2.00GHz
[DEBUG] CPU: ID a06a0, MeteorLake A0, ucode: 80000018
[DEBUG] CPU: AES supported, TXT supported, VT supported
[DEBUG] MCH: device id 7d02 (rev 00) is MeteorLake P
[DEBUG] PCH: device id 7e01 (rev 00) is MeteorLake SOC␛␛[DEBUG] IGD: device id ffff (rev ff) is Unknown
[INFO ] PMC: Using default GPE route.
[INFO ] VBNV: CMOS invalid, restoring from flash
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x1804000.
[DEBUG] FMAP: base = 0x0 size = 0x2000000 #areas = 33
[DEBUG] FMAP: area RW_NVRAM found @ 112b000 (24576 bytes)
[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8485b195f77225d8870589ff2e4d3dbdc8931f0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Base code is based of Intel Alder Lake SOC code.
List of changes:
1. Add required Meteor Lake SoC programming till bootblock
2. Include only required headers into include/soc
3. Include MTL-P related DID, BDF
4. Ref: Processor EDS documents
vol1 #621483, vol2 #640858
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Since the non-volatile storage as it handles VBNV storage in either
flash or CMOS, is chosen based on board design, removing VBOOT_VBNV_CMOS
& VBOOT_VBNV_CMOS_BACKUP_TO_FLASH from EHL soc kconfig.
Will add the option to EHL CRB mainboard kconfig later.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I97fb7017bff7751d64571d1a8ee7c8b9e2771731
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64473
Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch fixes the return type for `devfn` variable inside
heci_set_to_d0i3(). `PCI_DEVFN` macro returns `unsigned int`
instead of `pci_devfn_t`.
TEST=Able to build and boot to ChromeOS without any failure.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib3a575aa7d71cbe6932e823917b57c5558387433
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This patch renames heci_init() to cse_init() as HECI initialization
should have a bigger scope than just initializing the CSE
(a.k.a HECI1 alone).
BUG=none
TEST=Able to build and boot google/taeko.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic7edd55ccdcd70b244615fa06f81803a0ae6ce80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This patch removes the MTL CNVi DIDs macros from IA common code and is
added into the generic wifi driver.
As per Intel Connectivity Platform BIOS Guide, Connectivity Controller
IP for MTL-P is `Magnetar` and supported CRF is `Typhoon Peak 2`.
Previously Garfield Peak DIDs for Alder Lake SoC also added similarly
to generic wifi drivers.
BUG=b:224325352
TEST=Able to build and boot on MTL emulator.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib98762749c71f63df3e8d03be910539469359c68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
gpio_configure_pad function gets called for most of the GPIO
configuration for all the boards. This function is not handling NULL
pointers properly which can cause exception in CPU.
This patch fixes the handling and function is able to return early
in case the NULL pointer is passed or any subsequent child function
calls return NULL.
BUG=None
BRANCH=None
TEST=Compilation works fine for all Alder Lake boards.
Change-Id: I97fad72cdd92f70c7c5e6fdd23fbecf535a6e388
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Since of moving RAPL disabling to common code a config switch is
available to select that RAPL disabling has to be done via MCHBAR.
This patch selects the switch for EHL.
Test: Boot mc_ehl1 and ensure that relevant bits in MCHBAR are the same
as before the patch.
Change-Id: I1d0b7f650aa3ccf89c5c35d9b60a83a1ce48c74f
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch brings the feature of disabling RAPL to common code. It
replaces the current solution for APL and EHL.
For special case if RAPL disabling is only working via changes in MCHBAR
a new config switch was introduced.
Test: Boot mc_apl4/5 with this patch and ensure that the
relevant bits in MSR 0x610 are the same as before the
patch.
Change-Id: I2098ddcd2f19e3ebd87ef00c544e1427674f5e84
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch adds support for the ADL-N SKUs based on the PCH ID.
Document reference: 645548 (ADL-N EDS Volume 1).
BUG=None
BRANCH=None
TEST=Build FW and test on adln_rvp board
Change-Id: I24c18a27a4a2c68c78bc3dc728c45ba04f57205d
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64472
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This patch implements a SoC overrides to set CPU privilege level
as the MSR is not consistent across platforms. For example:
On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151.
BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4584516102560e6bb2a4ae8c0d036be40ed96990
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
mtrr_use_temp_range is a lot smarter than the plain set_var_mtrr. It
will compute a new optimal solution with the temp ranges included
while also taking care of the cleanup before loading the payload/s3
resume.
Change-Id: I283ba07fc12c410be39dfdc828657598237247c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63550
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch uses coreboot error codes instead of uint8_t data type in the
pre_mem_debug_init function.
TEST=build code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I957ff764900cb789bf2aacf0472dcb281f48af07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Based on the constraints for CML.
Fixes the following warnings in Linux on system76/oryp8 and
system76/gaze16, which have an NVIDIA GPU on the bridge.
pcieport 0000:00:01.0: can't derive routing for PCI INT A
pcieport 0000:00:01.0: can't derive routing for PCI INT B
This, in turn, resolves an IRQ conflict with the PCH HDA device that
would cause a stack trace on every boot and on S3 suspend.
irq 10: nobody cared (try booting with the "irqpoll" option)
<snip>
[<00000000fb84c354>] azx_interrupt [snd_hda_codec]
Disabling IRQ #10
Change-Id: Ibc968aaa7bf0259879097ff69d2543dcfa2e5e4b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or overriden
by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.
Change-Id: I520a936b4c3a8997ba2c6bea0126b3bbcc5d68ce
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or overriden
by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.
Also, remove related code from the mainboard starlabs/laptop/tgl, since
it is obsolete now.
Change-Id: I49bbd4a776b4e6c55cb373bbf88a3ca076342e3e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or overriden
by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.
Also, remove related code from the following mainboards, since it is
obsolete now.
* siemens/chili
* starlabs/laptop/cml
Change-Id: I173b87da5ce76549672c50ba30204cd77be8b82f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Move the Kconfig option `FSP_HYPERTHREADING` to common Intel Kconfig so
that it can be reused by other SoCs. Since not all SoCs support
hyperthreading, make it conditional on `HAVE_HYPERTHREADING`. SoCs
supporting hyperthreading need to select it so that `FSP_HYPERTHREADING`
is available.
Change-Id: I892d48b488cbf828057f0e9be9edc4352c58bbe7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The patch skips sending DISCONNECT IPC command to PMC if system resumes
from S3.
coreboot notice DISCONNECT IPC command getting timedout during S3
resume if system has AC connected behind Type-C hub. This impacts
system resume time. Please refer TA# 730910 for more information.
coreboot need not send the DISCONNECT IPC command when system resumes
from S3 state.
TEST=Verified system boots to OS and verfied below tests on Gimble
1. coreboot doesn't send the DISCONNECT during S3 resume
2. After S3 resume, system detects the pen drive with Superspeed
3. After system resumes from S3, hot-plug the pen drive, system detects
the pen drive
3. System sends IPC commands when system boots from S0 or S5.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I6ad006ae8677919c7dfeca8eec0af11454a2e89d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The FSP includes a UPD to set the DPA (Dynamic Periodicity
Alteration) PreWake value, which can be used to set the maximum
pre-wake randomization time in "micro-ticks". This patch adds
support for configuring that value.
BUG=b:228410327
TEST=build FW and checked DPA value by fsp log.
Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I08897c590a88aba058cb9e364185ea0794e1e7c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch drops the unused `PCH_DEV_SLOT_LPC` macro from the
Tiger Lake SoC PCI device list.
BUG=none
TEST=Able to build and boot volteer, google board.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I27a2f31aa706c4d76e9f0db202422bc129368959
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
All targets now use cbmem for the BERT region, so the implementation can
be common.
This also drops the obsolete comment about the need to have bert in a
reserved region (cbmem gets fixed to be in a reserved region).
Change-Id: I6f33d9e05a02492a1c91fb7af94aadaa9acd2931
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since the FIT pointer is patched at runtime there is no guarantee that
the pre-defined one will match the patched one. Add a check and print a
warning at runtime if both addresses (pre-defined and patched) do not
match as in this case an offline computed hash for the bootblock will
differ from the runtime one.
Change-Id: Ib1b02ec43af183caa9f5b08b3c485879b423c40f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Before TXE releases the CPU out of reset a pointer to the constructed
FIT in SRAM is patched into the loaded bootblock at offset 4G - 64B.
Since this patched bootblock gets measured during runtime it will not
match the one that is potentially measured from the coreboot image.
This patch adds a dedicated fit.c file for Apollo Lake where the FIT
pointer is already set to the address TXE will be using at runtime.
Test=Compare sha256 sum from coreboot runtime and coreboot.rom of the
bootblock and make sure they match.
Change-Id: Ia0fd2a19517c70f50ef37e6a2dc2408bae28df10
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
On Apollo Lake the bootblock is stitched into the IBBL IFWI region at
build time. At execution time TXE loads this IBBL into a shared SRAM
(which is read-only in this phase) and maps it at 4 GiB - 32 KiB. Then
the CPU starts to operate from this shared SRAM as it were flash space.
In order to provide a reliable CRTM init, the real executed bootblock
code needs to be measured into TPM if VBOOT is selected. This patch adds
the needed code to do this.
Change-Id: Ifb3f798de638a85029ebfe0d1b65770029297db3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
On platforms where the bootblock is not included in CBFS anymore
(because it is part of another firmware section (IFWI or a different
CBFS), the CRTM measurement fails.
This patch adds a new function to provide a way at SoC level to measure
the bootblock. Following patches will add functionality to retrieve the
bootblock from the SoC related location and measure it from there.
In this way the really executed code will be measured.
Change-Id: I6d0da1e95a9588eb5228f63151bb04bfccfcf04b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add the boot flash MMIO window to the resources to report this region as
reserved to the OS. This is done to stay consistent with the reserved
memory ranges by coreboot and make the OS aware of them.
As x86 systems preserves the upper 16 MiB below 4G for BIOS flash
decoding use the complete window for reporting independent of the
actually used SPI flash size. This will block the preserved MMIO window.
Change-Id: Ib3a77e9233c3c63bad4de926670edb4545ceaddf
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch drops the unused `PCH_DEV_SLOT_LPC` macro from the
Alder Lake SoC PCI device list.
BUG=none
TEST=Able to build and boot taeko, google board.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib2ae40fcc4499de34534f27f03b4c359c37409e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Since the fast SPI controller is hidden on Apollo Lake the OS cannot
probe it and is therefore unaware of the reserved resources assigned in
coreboot. Select 'FAST_SPI_GENERATE_SSDT' to enable SSDT creation to
report the reserved resources to the OS.
Change-Id: I23e77a0a01141dc4f299988d19509e6df555a654
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This patch provides the possibility for EHL based boards to disable
RAPL settings via SOC_INTEL_DISABLE_POWER_LIMITS config switch.
On Elkhart Lake the way via setting relevant MSR bits does not work.
Therefore the way via MCHBAR is choosen.
Test:
Check MCHBAR mapped registers (MCH_PKG_POWER_LIMIT) on mc_ehl1.
Change-Id: I5be6632b15ab8e14a21b5cd35152f82fec919d9f
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
EHL MAC side expects a rising edge signal for an IRQ. Based on the
mainboard wiring it could be necessary to change the interrupt polarity.
This patch provides the functionality to invert a falling edge signal
that comes from an external PHY. The inverting can be activated via
devicetree parameter.
Change-Id: Ia314014c7cacbeb72629c773c8c0bb5f002a3f54
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Hook Timer8254ClkSetting to `legacy_8254_timer` cmos option. If that
isn't set, fallback to the `USE_LEGACY_8254_TIMER` Kconfig option.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4f91cc2c8f48e9da47399059386092314b631b08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
If the SPI controller is hidden from the OS (which is default on Apollo
Lake) then OS has no chance to probe the device and therefore can not be
aware of the resources this PCI device occupies. If the OS needs to move
some resources for a reason it can happen that the new allocated window
will be shadowed by the hidden PCI device resource and hence causing a
conflict. As a result this MMIO window will be inaccessible from the OS
which will cause issues in applications. For instance on Apollo Lake
this causes flashrom to stop working.
This patch adds a SSDT extension for the PCI device if it is hidden from
the OS and reports the occupied resource via ACPI to the OS. For the
cases where the device is hidden later at coreboot runtime and therefore
is not marked as hidden in the PCI device itself a Kconfig switch called
'FAST_SPI_GENERATE_SSDT' is introduced. It defaults to 'no' and can be
set from SOC code to override it.
Since there is no defined ACPI ID for the fast SPI controller available
now, the generic one (PNP0C02) is used.
Test: Boot mc_apl4 and make sure flashrom works again.
Change-Id: Ia16dfe6e001188aad26418afe0f04c53ecfd56f1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Use defines for a better reading of the code.
Change-Id: I8e696240d649c0ea2341b8f04b62eebffebc1d57
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64519
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
By right if PseTsnGbeSgmiiEnable is disable,
PseTsnGbePhyInterfaceType should use RGMII setting.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: If593a5534716a9e93f99cb155fb5e86e12b1df17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
There are efforts to have bootflows that do not follow a traditional
bootblock-romstage-postcar-ramstage model. As part of that CBMEM
initialisation hooks will need to move from romstage to bootblock.
The interface towards platforms and drivers will change to use one of
CBMEM_CREATION_HOOK() or CBMEM_READY_HOOK(). Former will only be called
in the first stage with CBMEM available.
Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
