coreboot/src/soc/intel
Subrata Banik 6299cecb0d soc/intel/tigerlake: Drop unused PCH_DEV_SLOT_LPC macro
This patch drops the unused `PCH_DEV_SLOT_LPC` macro from the
Tiger Lake SoC PCI device list.

BUG=none
TEST=Able to build and boot volteer, google board.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I27a2f31aa706c4d76e9f0db202422bc129368959
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-05-25 18:08:06 +00:00
..
alderlake soc/intel/alderlake: Drop unused PCH_DEV_SLOT_LPC macro 2022-05-24 05:09:25 +00:00
apollolake soc/intel/apollolake: Compare patched FIT pointer with the pre-defined 2022-05-24 13:48:37 +00:00
baytrail CBMEM: Change declarations for initialization hooks 2022-05-20 07:15:39 +00:00
braswell CBMEM: Change declarations for initialization hooks 2022-05-20 07:15:39 +00:00
broadwell CBMEM: Change declarations for initialization hooks 2022-05-20 07:15:39 +00:00
cannonlake soc/intel/*: Use SSDT to pass A4GB and A4GS 2022-05-16 06:53:46 +00:00
common arch/x86/acpi_bert_storage.c: Use a common implementation 2022-05-25 12:51:32 +00:00
denverton_ns soc/intel/denverton_ns: Remove always false statement 2022-05-13 11:00:21 +00:00
elkhartlake soc/intel/elkhartlake/systemagent: Disable RAPL based on Kconfig 2022-05-23 07:17:21 +00:00
icelake soc/intel/*: Use SSDT to pass A4GB and A4GS 2022-05-16 06:53:46 +00:00
jasperlake soc/intel/*: Use SSDT to pass A4GB and A4GS 2022-05-16 06:53:46 +00:00
quark CBMEM: Change declarations for initialization hooks 2022-05-20 07:15:39 +00:00
skylake soc/intel/skylake: Hook up FSP hyper-threading setting to option API 2022-05-17 12:57:15 +00:00
tigerlake soc/intel/tigerlake: Drop unused PCH_DEV_SLOT_LPC macro 2022-05-25 18:08:06 +00:00
xeon_sp soc/intel/xeon_sp: Remove set but unused variable 2022-05-13 11:02:55 +00:00
Kconfig
Makefile.inc soc/intel/common/cse: Add support for stitching CSE components 2021-10-19 16:09:08 +00:00