erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

soc/intel/tgl: Add PEG devices to PCI constraints

Browse source 
Based on the constraints for CML.

Fixes the following warnings in Linux on system76/oryp8 and
system76/gaze16, which have an NVIDIA GPU on the bridge.

    pcieport 0000:00:01.0: can't derive routing for PCI INT A
    pcieport 0000:00:01.0: can't derive routing for PCI INT B

This, in turn, resolves an IRQ conflict with the PCH HDA device that
would cause a stack trace on every boot and on S3 suspend.

    irq 10: nobody cared (try booting with the "irqpoll" option)
    <snip>
    [<00000000fb84c354>] azx_interrupt [snd_hda_codec]
    Disabling IRQ #10

Change-Id: Ibc968aaa7bf0259879097ff69d2543dcfa2e5e4b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Tim Crawford 2022-05-25 12:36:47 -06:00 • committed by Martin L Roth
commit 59609784f0
1 changed files with 8 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

8
src/soc/intel/tigerlake/fsp_params.c
View file

@ -93,6 +93,14 @@ static void parse_devicetree(FSP_S_CONFIG *params)
* regardless of whether or not they are used by the mainboard.
*/
static const struct slot_irq_constraints irq_constraints[] = {
{
.slot = SA_DEV_SLOT_PEG,
.fns = {
FIXED_INT_PIRQ(SA_DEVFN_PEG1, PCI_INT_A, PIRQ_A),
FIXED_INT_PIRQ(SA_DEVFN_PEG2, PCI_INT_B, PIRQ_B),
FIXED_INT_PIRQ(SA_DEVFN_PEG3, PCI_INT_C, PIRQ_C),
},
},
{
.slot = SA_DEV_SLOT_IGD,
.fns = {