Add camera related support
* Enable the SA Imaging Unit and CIO2 devices.
* Enable TPS68470 PMIC and populate related ACPI objects.
* Enable OV cameras and populate related ACPI objects.
* Enable Dongwoon AF DAC and populate related ACPI objects.
BUG=b:36580624
BRANCH=none
TEST=Build and boot poppy. Dump and verify that ACPI tables
have the required entries for all the camera devices.
Change-Id: I6d3db52880f4c53e5205e52080318826fe32b280
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 35e6eb1cef
Original-Change-Id: Ifbe878bb6b25fc976e935fee16c4d59fadd47fe2
Original-Signed-off-by: Sowmya V <v.sowmya@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18969
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/482962
This patch includes ipu.asl file in the main DSDT definition
to add ACPI entries for IMGU and CIO2 devices.
BUG=b:36580624
BRANCH=none
TEST=Build and boot poppy. Dump and verify that DSDT table
has the entries for IMGU and CIO2 devices.
Change-Id: If49ae5e9f6c9b9aa07071520bedc0ea1dd970086
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fa7d0a857d
Original-Change-Id: Ib7485315cb9468da7c6aa090862657a265121493
Original-Signed-off-by: Sowmya V <v.sowmya@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19110
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/482960
1. Update formatting of gpio table to fit everything within 80 column
limit.
2. PEN_RESET gpio is non-existent. Get rid of it.
BUG=b:37375693
Change-Id: I533cb16fb3bbc75799340879614bbecc1aafee14
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e0f30920f0
Original-Change-Id: I1bcc4168659f365547e5f7227df8659e4bc7f243
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19320
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/481282
Enable lower power state when running on battery. Deep S3 is not
enabled when in AC mode to support standard "docked" config.
BUG=b:36087058,b:36723679
TEST=Verified following behavior with USB mouse:
1. If AC is connected when entering S3, USB mouse is able to wake up.
2. If AC is not connected when entering S3, USB mouse does not wake up.
3. If AC is connected when entering S3 and removed after entering S3,
USB mouse does not wake up.
4. If AC is not connected when entering S3 and attached after entering
S3, USB mouse does not wake up.
Change-Id: Ie0d0063c572d7b516bb556d6ef38a10eebd02bd5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 55d9c0bd8d
Original-Change-Id: I141a8d4779de004e27fcd9357cef787a38a27b24
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19276
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/481281
TPM ACPI entries are automatically generated, and the old static
TPM ASL file is obsolete. Remove the reference to this obsolete
static ASL file.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6a18dadf01707bc8236a506d1e90d10d4274b75f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eca093ecfe
Original-Change-Id: I3cb2a8a3ac337d1de8a3c394d7a28155597239d0
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/19283
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-on: https://chromium-review.googlesource.com/480298
Commit bf264e94 (i945:) adds a PCI reset to the romstage, and commit
bc8613ec (Fix i945 based boards) fixes that to use the correct
delay of 200 ms. This code was then copied over, when adding support for
the Lenovo T60.
The reset was related to the shipped crypto card on the Roda RK886EX and
Kontron 986LCD-M, so is not needed on the Lenovo T60. So remove it, to
reduce the boot time by 200 ms.
The same change is done for the Lenovo X60 in commit 7676730b
(mb/lenovo/x60: Remove PCI reset code from romstage).
BUG=none
BRANCH=none
TEST=none
Change-Id: I1eb34bad5b378dcdfca130ec54cf3252affc53f8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 79a27ac8b8
Original-Change-Id: Ifff43f095a1236c9e9a9ef0687e8efe42e72c971
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/19298
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/480296
The HDA verb for falco/wolf's internal mic was wrong, preventing the mic
from working properly in Windows and macOS (the Linux driver overrides
the verb table, so wasn't affected). Set the verb connector/jack bits
properly, to no connector / no jack detect, in order to fix.
Also, make (2) small non-functional fixes:
On falco, NID 0x1A was being disabled twice (instead of 0x1A and 0x1B
both being disabled - copy/paste error).
On wolf, NID 0x19 was set to an internal analog mic, where it should have
been disabled (again, copy/paste error).
Both these errors were introduced when consolidating/upstreaming
and were not present in the original Chromium sources.
Test: boot Windows [8/8.1/10] and verify mic functional with Realtek
drivers on both falco and wolf.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibf026149b4ca2e28954cdd1d9e3c24bebfc63a57
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6fa36c9c2c
Original-Change-Id: I9c343dda4762f0b1f814318c155e22c59d2da8db
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19262
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480291
Remove the 'probed' setting from the Realtek 5663 headset codec I2C
device. This was added when we had a hardware issue that was preventing
I2C operation because the clock/data lines were swapped.
With new and/or reworked hardware this is no longer a problem and we do
not want the I2C layer in the kernel to talk to the device before the
rt5663 driver.
BUG=b:35585307
BRANCH=none
TEST=Boot on Eve and verify rt5663 driver still loads properly.
Change-Id: I861c3a451b70127fb43f4688871daaaee4507fce
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 241c4f244f
Original-Change-Id: Ice38889e8f5d3fd1307056cab10fbe3f4e197749
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19304
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/480287
Use linker instead of '#include *.c'.
The smbus_fixup() was changed not to use a structure that's defined by a
northbridge since multiple different northbridges can be used. Instead
the caller now directly passed the memory slot details.
BUG=none
BRANCH=none
TEST=none
Change-Id: I247296dd5c3bd6fe59a74280a98a7d4fcf09d991
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b0161fd2d8
Original-Change-Id: Ia369ece6365accbc531736fc463c713bbc134807
Original-Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Original-Reviewed-on: https://review.coreboot.org/19082
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/480281
Remove the ACPI ALS device from the EC configuration because this system
has an ALS that is presented through the new EC sensor interface rather
than the legacy ACPI interface.
BUG=b:37179776
BRANCH=none
TEST=Boot an Eve device and ensure that 'acpi-als' device is not present
in /sys/bus/iio/devices.
Change-Id: Idd98d9faf54db5fea2265ed54c358d284d45c03d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f13e250152
Original-Change-Id: Ie18b8a661e4d16464784ca8a227586036e7631de
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19265
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/480103
Set UART0 to "PchSerialIoSkipInit" so the pins for this device are not
set back to native mode by FSP when configured as GPIO input by coreboot.
Now that FSP is not touching the pins I also removed the workaround to
reconfigure the pins after FSP.
BUG=b:35647877
BRANCH=none
TEST=Verify that GPP_C8-GPP_C11 are configured as GPIO input once the OS
is booted and they are not set back to native function by FSP.
Change-Id: I688433e8b6556c5f3e2c374481cd29d8351c0032
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e49b866c7c
Original-Change-Id: Ifec4fa3e66ceeb660bad00c66bc7bd44bb457a01
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19264
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480102
These lines act as inputs to both EC and AP and when the corresponding
TCPC mux is in low power mode the line is floating. Add an internal
pull-down to each GPIO to prevent it from floating in this state.
BUG=b:35775012
BRANCH=none
TEST=Verify that the kernel does not see a device present on DP when
the TCPC mux is in low power mode.
Change-Id: I6d940004364e4a5cc338ff2063d034d12c1dcf88
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 30783d84cf
Original-Change-Id: Ie229f84871e9994467c0ab660cc7e271a51d9cbb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19263
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480101
With EuP and PME enabled the USB power turns off during S5.
BUG=none
BRANCH=none
TEST=none
Change-Id: I57d70a85586832384e5c6fc9d65a681404b7a48a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5ad939679f
Original-Change-Id: I8b9fd7bb308f544401f90f8aa5ffaec61251b2b3
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/19073
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/480100
In order to support a standard "docked" config disable Deep S3 when
connected to AC power. This allows USB devices to wake the device
from suspend if it is externally powered, but still retains the
lower power state when running on battery.
BUG=b:36723679
BRANCH=none
TEST=manual testing on Eve for USB wake behavior:
1) when suspended on battery USB keyboard does not wake
2) when suspended while connected to AC a USB keyboard does wake
3) if suspended with AC, and then AC is removed, system does not
wake with USB keyboard
4) if suspended without AC, and then AC is added, system does not
wake with USB keyboard (it cannot get enabled without waking and
re-suspending)
Change-Id: I522b50c16fa0c4c3ba3731075fe29d3e799935d4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 73ff0fbd2e
Original-Change-Id: I670e39d42cdb5b80612206da899be82ef3b2cbf2
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19240
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/480098
Enable the Intel WiFi SAR feature for Eve, which will be used to
provide wifi power tables based on values read from VPD.
This is enabled based on CONFIG_CHROMEOS because it relies on the
presence of VPD code from vendorcode/google/chromeos.
BUG=b:36727652
BRANCH=none
TEST=test on Eve by setting "wifi_sar" in VPD and ensuring that
the ACPI WIFI device gets the expected "WRDS" and "EWRD" tables
with the values that were set in VPD.
Change-Id: I124395715f3b074c74ce8b9436b561143aceac46
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 654c8de9f1
Original-Change-Id: I11c129baca891221177575108ac09ba1707b516e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19241
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/480097
Currently when enabling Deep S3 or Deep S5 it unconditionally gets enabled
in both DC and AC states. However since using Deep S3 disables some
expected features like wake-on-USB it is not always desired to enable the
same state in both modes.
To address this split the setting and add a separate config for Deep Sx in
AC and DC states.
All motherboards that set this config were updated, but there is no actual
change in behavior in this commit.
BUG=b:36723679
BRANCH=none
TEST=This commit has no runtime visible changes, I verified on Eve that the
Deep SX config registers are unchanged, and it compiles for all affected boards.
Change-Id: Ifceb6039323c6a755ea4a0c26356aa778e2d04d1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1fe32d6bb2
Original-Change-Id: I590f145847785b5a7687f235304e988888fcea8a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19239
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/480096
These lines act as inputs to both EC and AP. Thus, add internal
pull-downs to prevent them from floating.
BUG=b:35648530
Change-Id: Ia73ecfe432c5543d37d5ff166124d364006138ae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bcbba801b8
Original-Change-Id: I42326c810775d5449e99e52e81870970247ce335
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19243
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/480095
Put all configs required for enabling cr50 SPI TPM on poppy under
POPPY_USE_SPI_TPM so that it can be enabled any time for testing SPI
TPM on this board.
Also, add required callback for irq status and devicetree config for
GSPI0.
BUG=b:36873582
Change-Id: Ie467753b802ccce1d50c5a982da77872ac274f30
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 82010835bf
Original-Change-Id: I67793093c006c1325fc16f669a96126525f83243
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19238
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/480094
Scarlet don't have eDP and MIPI driver is not ready, skipping
display for now or else Scarlet would be stuck in
reading eDP HPD because there even not power for it.
TEST=boot to kernel on Scarlet
Change-Id: Id2558eeb60900a25f2c99c42b338db2d9d80fd57
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4f4410dcbc
Original-Change-Id: I02ab4ef21bf77b98414f537aca57b46c11922348
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19237
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/474137
Due to issues with stability limit the SKU with K4EBE304EB-EGCF
memory to 1600MHz instead of 1866MHz.
BUG=b:37172778
BRANCH=none
TEST=pass stress testing on devices with this memory
Change-Id: I3dd16517ce8043d9a71e2da553f81861504a29ea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 08117c412c
Original-Change-Id: I02af7e9c35e2c5b0b85223d58025cbd29841d973
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19227
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/474136
This is needed if one wants to use the header more than once.
BUG=none
BRANCH=none
TEST=none
Change-Id: If43ac3dafbb8e6b9052d6af9206d586d5a466ce1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f170e71630
Original-Change-Id: I375d08465b6c64cd91e7563e3917764507d779ba
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19029
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/474135
Update the I2C rise/fall timings based on newly measured values
on a new board with updated pull-up resistor values.
Touchscreen: rise time 98ns, fall time 38ms
Touchpad: rise time 111ns, fall time 41ns
TPM: rise time 112ns, fall time 34ns
BUG=b:35583133
BRANCH=none
TEST=Each I2C bus frequency was verified on a scope to be ~400MHz
Change-Id: Ib2b0598fb10c3e0e21161583362fc317d3e1f5c9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 92dde2fdd7
Original-Change-Id: Ibb3a15fa0cc862f36c1b9c63ac7847221020c4c0
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19202
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/474127
This patch cleans up the code by:
o adding necessary default definitions to Kconfig
o removing incorrect definitions from devicetree
o removing irrelevant entries from FMD file
devicetree.cb and minnow3.fmd carried over a lot of code from google/reef
which is not correct for Minnow3 hardware. Minnow3 is not intended to
boot Chrome OS and does not need Chrome related flash regions. The
erroneous code is removed.
These changes are the same as those done for leafhill in commit:
6a48923 mainboard/intel/leafhill: Clean up
This was tested by building with the new configuration and
booting to UEFI Payload
BUG=none
BRANCH=none
TEST=none
Change-Id: I55cba41ba898e8e4f2b74805ae9cf5a391adc277
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 44ff10eaa6
Original-Change-Id: I620dcbcd622f9326917c74b2a38984d9e49cff2b
Original-Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18963
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/472713
This fixes the following issues, with no functional changes:
ERROR:POINTER_LOCATION: "foo * bar" should be "foo *bar"
ERROR:SPACING: space required after that ',' (ctx:VxV)
WARNING:LONG_LINE_COMMENT: line over 80 characters
WARNING:SPACE_BEFORE_TAB: please, no space before tabs
ERROR:FUNCTION_WITHOUT_ARGS: Bad function definition
ERROR:SPACING: space prohibited before that close parenthesis ')'
WARNING:RETURN_VOID: void function return statements are not generally
useful
2 unfixed issues:
ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
Verified that the binary was the same before and after the changes.
BUG=none
BRANCH=none
TEST=none
Change-Id: If7a8efa7bd02cb70eba10686396274d44953d6e9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9931f66581
Original-Change-Id: Ie9afb50e268f4140872e39fe8bede231a43d5cc6
Original-Signed-off-by: Martin Roth <gaumless@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19078
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/472712
All boards select INTEL_EDID, move it to nb folder.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie41e0d5dc6a50e9b2ba170cf1ad6c25b74a47f2e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 46cf5c29b3
Original-Change-Id: I35f075a87f2d841856b208f9440cf41af6a3c8e6
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19086
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/472711
Linking should allow to link depending on possible future variants.
E.g. in Makefile.inc romstage-$(CONFIG_'VARIANT0') += gpio_variant0.c
etc.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifba4887fe5c212000bedd540e5f8ebf1f73c88e2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7dee97454a
Original-Change-Id: I88b5ef8e12ac606751952a493f626e1b146e98f7
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19139
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/471526
Add package options to the CPU Kconfig that may be selected by the
mainboard's Kconfig file. Stoney Ridge is available in FP4 and FT4
packages and each requires a unique binaryPI image. Default to the
correct blob used by the northbridge by looking at the CPU's package.
Also modify Gardenia to select the right package.
See the Infrastructure Roadmap for FP4 (#53555) and FT4 (#55349) for
additional details for the packages.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 7b8ed7b732b7cf5503862c5edc6537d672109aec)
BUG=none
BRANCH=none
TEST=none
Change-Id: I2fcb523d6cfef530fb7b2a9b9c7ca2e92a73297f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5995ee62f7
Original-Change-Id: I7bb15bc4c85c5b4d3d5a6c926c4bc346a282ef27
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18989
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/471465
The term 'callout' has a specific meaning in AGESA, meaning
invoking the said function from AGESA / PI proper.
OemPostParams() does not fall into that category.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3229eac2405617ecb6108f6ca7af4c5aecbd118a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 47f4cf87bd
Original-Change-Id: I0ad1cbf244501207af96e0ac415a5b80ced91052
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19141
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/471464
The term 'callout' has a specific meaning in AGESA, meaning
invoking the said function from AGESA / PI proper.
OemPostParams() does not fall into that category.
BUG=none
BRANCH=none
TEST=none
Change-Id: If0c450bc95283f5d180750100ca2a2064af04912
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 353293580e
Original-Change-Id: I45913d93323b3813fc35b1dd1fdca3d782d4b01f
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19140
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/471463
Even though the i2c spec has no minimum data hold time in fast
mode the trackpad vendor indicates 300ns is their minimum. However,
the topology of the board uses FET isolation to cross voltage
domains. Therefore, the default 300ns which should work isn't reflected
on the device side of the voltage isolation circuit. Therefore,
increase the data hold time to show an observed data hold time of
more than 300ns on the device side.
BUG=b:36469182
Change-Id: Ibf33401c55f4e3b34b7f236f26eda7dcf5fa3bf3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2fb5ca81d9
Original-Change-Id: I1b70f2f53c5a29cc7cfd5035a71ca5811b3bcba0
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19065
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/471453
BUG=b:35583511
BRANCH=gru
TEST=check i2c bus 0 initializes from ap console log
Change-Id: Ib45f90313852601e6a4f9e23b36bc6f46bb3f4d6
Signed-off-by: Philip Chen <philipchen@google.com>
Original-change-Id: Ibb6709159f5ed28ad0b62397d2ddb504dec55167
Original-signed-off-by: Philip Chen <philipchen@google.com>
Original-reviewed-on: https://review.coreboot.org/19105
Original-tested-by: build bot (Jenkins)
Original-reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/470566
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This mainboard uses a LVDS connection for LCD panels. Apollo Lake SoC
provides a display controller with three independent pipes (1x eDP and
2x DP/HDMI). PTN3460 is an embedded DisplayPort to LVDS bridge device
that enables connectivity between an eDP source and LVDS display panel
(http://www.nxp.com/documents/data_sheet/PTN3460.pdf).
The bridge contains an On-chip Extended Display Identification Data
(EDIT) emulation for EDIT data structures.
This patch sets up PTN3460 to be used with the appropriate LCD panel.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1b69b1411786343417bc49b43a1300315c0fe252
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 956a9f6a9c
Original-Change-Id: Ib8fa79bb608f1842f26c1af3d7bf4bb0513fa94d
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19043
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/467112
Wake On Voice stream capture configuration is mono. It is sufficient
to keep DMIC_CLK_A1 on in S0ix; so, turning off DMIC_CLK_B1.
Power saving should be visible in the boards which has more
than one DMIC connected.
BUG=None
BRANCH=None
TEST=WoV and quad channel DMIC capture works
Change-Id: Ide41768001b535141948d6d0290725ae29a744ba
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2e2370075d
Original-Change-Id: Ic46d4c7b30b945eba47a05d78386f48e4a675a03
Original-Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19018
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/462959
We define AGESA_LEGACY as an implementation of mainboard
that has its romstage main completely under mainboard/
directory. We have learnt from other platforms this approach
has several downsides when it comes to making platform-wide
improvements.
We start by creating per-family romstage.c file, which
boards will gradually take into use by removing the
AGESA_LEGACY Kconfig option we here apply to all of them.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3ff98b2ee71ee55883efe83372494d2181785388
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 967d94d626
Original-Change-Id: Id01931e185a023039a60af16a678de9966db8d65
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18619
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/462938
