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UPSTREAM: mb/lenovo/t60: Remove PCI reset code from romstage

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Commit bf264e94 (i945:) adds a PCI reset to the romstage, and commit
bc8613ec (Fix i945 based boards) fixes that to use the correct
delay of 200 ms. This code was then copied over, when adding support for
the Lenovo T60.

The reset was related to the shipped crypto card on the Roda RK886EX and
Kontron 986LCD-M, so is not needed on the Lenovo T60. So remove it, to
reduce the boot time by 200 ms.

The same change is done for the Lenovo X60 in commit 7676730b
(mb/lenovo/x60: Remove PCI reset code from romstage).

BUG=none
BRANCH=none
TEST=none

Change-Id: I1eb34bad5b378dcdfca130ec54cf3252affc53f8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 79a27ac8b8
Original-Change-Id: Ifff43f095a1236c9e9a9ef0687e8efe42e72c971
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/19298
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/480296
This commit is contained in:
Paul Menzel 2017-04-14 19:37:14 +02:00 • committed by chrome-bot
commit 815f2cf63a
1 changed files with 0 additions and 5 deletions
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5
src/mainboard/lenovo/t60/romstage.c
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@ -181,11 +181,6 @@ void mainboard_romstage_entry(unsigned long bist)
if (bist == 0)
enable_lapic();
/* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
udelay(200 * 1000);
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
ich7_enable_lpc();
/* We want early GPIO setup, to be able to detect legacy I/O module */