Some changes were made in upstream in the meantime that broke the build:
- CHROMEOS_VBNV_CMOS was renamed to VBOOT_VBNV_CMOS
- recovery_move_enabled() -> vboot_recovery_mode_enabled()
- chromeos.asl was replaced by an acpi generator
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/16683
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: Icd4ed5111cce9db79e12efb0cb7e898bba725c20
Reviewed-on: https://chromium-review.googlesource.com/388319
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Migrate google/enguarde (Lenovo N21 Chromebook) from Chromium tree to
upstream, using google/rambi as a reference.
original source:
branch firmware-enguarde-5216.201.B
commit cf1f57b [Enguarde: Adjust rx delay for norm.]
TEST=built and booted Linux on enguarde with full functionality
blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.elf)
external reference code (refcode.elf)
BUG=None
BRANCH=None
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/15444
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I3ccda29d1e095d8b1b36766cda913172f72233a7
Reviewed-on: https://chromium-review.googlesource.com/388317
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during
verstage. The interrupt is left in APIC mode as the GPE is
still latched when the GPIO is pulled low.
BUG=chrome-os-partner:53336
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16673
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ib0247653bdcbaccb645cd16b81d7ec3c38f669af
Reviewed-on: https://chromium-review.googlesource.com/388313
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This implements PRW method for WLAN and configures PCIe wake pin to
generate SCI.
BUG=chrome-os-partner:56483
BRANCH=None
TEST=Suspend the system into S3 or S0ix. System should resume through wake
event from wifi.
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16611
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I9bd078c2de19ebcc652b5d981997d2a5b5f0b1b7
Reviewed-on: https://chromium-review.googlesource.com/388113
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It will enable PHY_PER_CS_TRAINING when DDR DDR frequency >= 666.
For per cs training, the controller should consider the PHY delay
line switch time,there should be more cycles to switch delay line.
So need increase W2W_DIFFCS_DLY_ value from 0x1 to 0x5.
BRANCH=none
BUG=chrome-os-partner:56940
TEST=do memtester on kevin board, and pass
Change-Id: I81b99cbc085769b7028e770509d79bd8d550820b
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/387506
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
for save power consumption, some gpio2 ~ gpio4 need to
set to input and pull none mode. It depend on these gpio
should shut down there power supply, so pass apio number
to ATF, to decide which gpio need to config.
BRANCH=None
BUG=chrome-os-partner:56423
TEST=run suspend_stress_test on kevin board
Change-Id: Iaf441e8e34c5591ffe7c65f6533fcf0b733ff5ac
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/378475
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
we need to disable some regulator when device into suspend,
it mean we need to pass some gpio to bl31, and disable these
gpios when bl31 run suspend function.
BRANCH=None
BUG=chrome-os-partner:56423
TEST=enter suspend, measure suspend gpio go to low
Change-Id: I03d0407e0ef035823519a997534dcfea078a7ccd
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/374046
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
There are certain board-specific options for reef variants. The
big one is the DPTF settings. Rearrange the ASL files such
that dsdt.asl is the main landing area. The ACPI options for
Chrome EC are contained in the variant/ec.h header so the
actual code #includes can just reside in dstd.asl. Since most
of the mainboard specific peripherals are auto generated by
the acpigen from devicetree there's no real separate need
for mainboard.asl. The one thing not addressed in this CL
is the notion of a variant having the Chrome EC or not (along
with lid, etc). Future indirection can be provided when needed
to address that requirement.
BUG=chrome-os-partner:56677
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16604
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I5c888f5fc64913dcff010c28f87e69ac5449e6b6
Reviewed-on: https://chromium-review.googlesource.com/386299
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch removes setting of gpio_tier1_sci_en from mainboard
smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
now.
BUG=chrome-os-partner:56483
BRANCH=None
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
Also from S0iX system is resuming for WIFI wake.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16566
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I26fd3fd9fcc83c988bcff1bda4da7a2e3da98ce6
Reviewed-on: https://chromium-review.googlesource.com/385902
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch sets tuned RAPL power limit PL1 value to
12W in acpi/dptf.asl for RAPL MSR register. With PL1
as 12W for WebGL and stream case, we measured SoC power
reaching upto 6W. Above 12W PL1 value, we observed that
Soc power going above 6W. With PL1 as 12W, system is
able to leverage full TDP capacity.
BUG=chrome-os-partner:56524
BRANCH=None
TEST=Built, booted on reef and verifed the package
power with heavy workload.
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/16596
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I8185ce890f27e29bc138ea568af536bc274fe7b8
Reviewed-on: https://chromium-review.googlesource.com/385093
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This configures PERST_0 in devicetree. For boards without
PERST_0, the pin should be disabled. For boards with PERST_0
the correct GPIO needs to be assigned.
BUG=chrome-os-partner:55877
BRANCH=None
TEST=None
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16603
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Change-Id: I705009b480e02b4c9b2070bb4f82cb4d552e9a46
Reviewed-on: https://chromium-review.googlesource.com/385092
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add MKBP as a SCI event: the EC is then able to send events coming from
the sensors.
BUG=b:27849483
BRANCH=None
TEST=With EC configure to send MKBP events, check sensor information are
retrieved by the kernel.
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/16594
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ib06241bfcdc8567769baff4f3371cc0c6eab3944
Reviewed-on: https://chromium-review.googlesource.com/384341
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Gwendal Grignou <gwendal@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
To improve sdram 800MHz and 933MHz stability, we
need to modify write leveling flow, to get the
more proper write leveling value.
BUG=chrome-os-partner:56940
BRANCH=none
TEST=Boot from kevin on 933MHz, and do stressapptest
Change-Id: I87efddf628c3683fcb85d6875e029cf3cbc482be
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/384292
Commit-Ready: Julius Werner <jwerner@chromium.org>
Tested-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Since there's currently a limitation in coreboot's code that prevents
more than 4KB to be used by the eventlog anyway, this patch shrinks the
available RW_ELOG area in the FMAP for Gru down to 4KB. This may prove
prudent later if we ever resolve that limitation, so that tools can rely
on the area in the FMAP being the same as the area actually used by the
read-only firmware code on these boards.
BRANCH=gru
BUG=chrome-os-partner:55593
TEST=Booted Kevin, confirmed that eventlog got written normally. Ran a
reboot loop to exhaust eventlog space, confirmed that the shrink code
kicks in as expected before reaching 4KB.
Change-Id: Ia2617681f9394e953f5beb4abf419fe8d97e6d3e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/384585
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Simon Glass <sjg@google.com>
This driver is only a prototype driver, real driver
will be integrated at a later time.
Testing: booted successfully.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/16554
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I372764962e96e5c9c827d524bc369978c5c1fda8
Reviewed-on: https://chromium-review.googlesource.com/384988
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Several of the special function pins we're using in firmware have a
pre-assigned pull-up or pull-down on power-on reset. We don't want those
to interfere with any of the signaling we're trying to do on those pins,
so this patch disables them.
Also do some house-cleaning to group the bootblock code better, and
change the setup code for all SPI and I2C buses to first initialize the
controller and then mux the pins... I assume this might be a little
safer (in case the controller peripheral has some pins in a weird state
before it gets fully initialized, we don't want to mux it through too
early).
BRANCH=None
BUG=chrome-os-partner:52526
TEST=Booted Kevin.
Change-Id: I6bcf2b9a5dc686f2b6f82bd80fc9a1a245661c47
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382532
Move the current devicetree.cb to be under variants/baseboard.
New variants can provide their own devicetree as needed.
BUG=chrome-os-partner:56677
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16510
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib109ca4be883884b318264500d14aa8d40e3072a
Reviewed-on: https://chromium-review.googlesource.com/382722
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
we found some board not stable when sdram run 933Mhz, before we fix
it, we need to lower down the sdram frequency to 800MHz. In this patch
we modify the DQS delay from 0x280 to 0x260, extend the DQS window.
BRANCH=None
BUG=chrome-os-partner:56940
TEST=Booted Kevin.
Change-Id: I5eab6bbe96f0dae095c5353403292022e7a25421
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/382724
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Increase the SPI bus speed to speed up boot time. The maximum supported
speed at 1.8V is 37.5MHz, and 33MHz is the next lowest convenient speed,
given the clock parents.
BUG=chrome-os-partner:56556
BRANCH=none
TEST=boot on gru and see that things still work correctly. Total time
spent on reading from SPI reduces from 185ms to 141ms.
Change-Id: I55a19f523817862e081d23469e94fd795456dd67
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/381313
Commit-Ready: Julius Werner <jwerner@chromium.org>
Tested-by: Simon Glass <sjg@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Enable the I2C based TPM on the reef board at
bus 2 and address 0x50.
This makes vboot functional without needing MOCK_TPM and
results in the following in the SSDT:
Device (TPMI)
{
Name (_HID, "GOOG0005") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_DDN, "I2C TPM") // _DDN: DOS Device Name
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
I2cSerialBus (0x0050, ControllerInitiated, 0x00061A80,
AddressingMode7Bit, "\\_SB.PCI0.I2C2",
0x00, ResourceConsumer)
Interrupt (ResourceConsumer, Edge, ActiveLow, Exclusive)
{
0x00000039
}
})
}
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16398
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia9775caabeac3e6a3bd72de38f9611b4cea7cea4
Reviewed-on: https://chromium-review.googlesource.com/382078
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If we setup the PWM _after_ the pinmux then there's a period of time
when we're driving the PWM incorrectly. Let's setup the regulator and
_then_ configure the pinmux.
This fixes no known bugs, but it is more correct and probably makes the
signals look better at bootup.
BRANCH=None
BUG=None
TEST=scope
Change-Id: I5124f48d04a18c07bbd2d54bc08ee001c9c7e8d1
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/381592
Reviewed-by: Simon Glass <sjg@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The pull up for CLKRUN is required to resolve keyboard slowness
and malfunctioning observed on some reef systems. The CLKRUN
signal was probed and found to be floating when the pull up
was not enabled. Also Added pull ups for the LPC Multiplexed
command, address and data lines LAD0:3 because the LPC
Interface specification requires them.
BUG=chrome-os-partner:55586
BRANCH=none
TEST=When a key is pressed, the character is immediately visible
on the screen. Also the interrupt count for i8042 increments
immediately in /proc/interrupts.
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/16426
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Change-Id: I16df1a0301a3994c926a609f61291761219f9e01
Reviewed-on: https://chromium-review.googlesource.com/381741
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The last vestige of the proto boards is the memory sku id
gpios. The internal pullups are still required because there's
only pulldown stuffing options available on the reef boards.
BUG=chrome-os-partner:56791
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16432
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: I04d541a897ec9aacbf2011293d18242fa32896d2
Reviewed-on: https://chromium-review.googlesource.com/381740
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the current NHLT configuration implementation to the baseboard
area such that other variants can leverage it or provide their
own configuration.
BUG=chrome-os-partner:56677
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16431
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: If0d48cacdc793492e1618d0eda02a149e33f0650
Reviewed-on: https://chromium-review.googlesource.com/381739
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the current memory configuration implementation to the baseboard
area such that other variants can leverage it. The swizzle config
is exported as a global to allow duplicate swizzles to use the same
structure while still allowing different memory SKUs.
BUG=chrome-os-partner:56677
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16430
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I57201118053051c01f0e3f164ab4bbaf650b892b
Reviewed-on: https://chromium-review.googlesource.com/381738
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since multiple boards will be living within one directory move all
the macros for defining anyting related to GPIOs to the gpio.h
header file. That way, when other boards land they can override
or use them as is.
BUG=chrome-os-partner:56677
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16421
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I36967e57fc61ef354e0b51d1ff1396ce562fa805
Reviewed-on: https://chromium-review.googlesource.com/381736
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There's no common EC header file in the code base, and I didn't
want to use a header file for single declaration. Therefore,
just move the declaration to each file that uses that symbol.
BUG=chrome-os-partner:56677
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16420
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ibaebb0ea6a07029aec02d5185cf05ffb8593b117
Reviewed-on: https://chromium-review.googlesource.com/381735
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add lpddr3-K4E6E304EB-2GB-1CH memory configuration for rialto.
BUG=chrome-os-partner:56759
BRANCH=none
TEST=Build
Change-Id: I7dae9fd822abeff5b08de0ab9262e1817ac58531
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/380443
Commit-Ready: Alexandru Stan <amstan@chromium.org>
Tested-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Jonathan Dixon <joth@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
To further the ability of multiple variant boards to share code
provide a place to land the split up changes. This patch provides
the tooling using a new Kconfig value, VARIANT_DIR, as well as
the Make plumbing. The directory layout with a single variant,
reef (which is also the baseboard), looks like this:
variants/baseboard - code
variants/baseboard/include/baseboard - headers
variants/reef - code
variants/reef/include/variant - headers
New boards would then add themselves under their board name
within the 'variants' directory.
No split has been done with providing different logic yet.
This is purely a organizational change.
BUG=chrome-os-partner:56677
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16418
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ib73a3c8a3729546257623171ef6d8fa7a9f16514
Reviewed-on: https://chromium-review.googlesource.com/381660
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of completely duplicating the a reference board's directory
when doing a variant or follower device start providing a means to
share code within a single directory. This change just starts the
process from the Kconfig side, but subsequent patches will follow
which disentangles the board specific pieces from and common
logic.
BUG=chrome-os-partner:56677
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16417
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I96628920d78012e488ec008e35daac9c1be0cf79
Reviewed-on: https://chromium-review.googlesource.com/381659
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The superio.asl wasn't being included within the right scope.
Fix that as well as clean up the per-mainboard header includes
to be in one place.
BUG=chrome-os-partner:56677
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16413
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I5e6a82f9f2e3c7455132263d19b32b2f06220376
Reviewed-on: https://chromium-review.googlesource.com/381658
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some of the macros in gpio.h are no longer used because
devicetree.cb is being used to autogeneric the ACPI AML.
Therefore remove the unused macros.
BUG=chrome-os-partner:56677
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16412
Tested-by: build bot (Jenkins)
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I433a929229a0318f6c1df652655d046a5152cc63
Reviewed-on: https://chromium-review.googlesource.com/381657
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch moves the big CPU cluster initialization on the RK3399 from
the clock init bootblock function into ramstage. We're only really doing
this to put the cluster into a sane state for the OS, we're never
actually taking it out of reset ourselves... so there's no reason to do
this so early.
Also cleaned up the interface for rkclk_configure_cpu() a bit to make it
more readable.
BRANCH=None
BUG=chrome-os-partner:54906
TEST=Booted Kevin.
Change-Id: Ic3d01a51531683b53e17addf1942441663a8ea40
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/377541
Reviewed-by: Douglas Anderson <dianders@chromium.org>
The following patch is based off of the UEFI 2.6 patch. The FSP header files
are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated
since the other headers expect it to be in the root of an includable directory.
Any struct defines were removed since they are defined in the headers and no
longer need to be explicity declared as struct with the UEFI 2.6 includes.
BUG=chrome-os-partner:54100
BRANCH=none
TEST=confirmed coreboot builds successfully
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>#
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16308
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7
Reviewed-on: https://chromium-review.googlesource.com/381007
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Many changes make proto boards very hard to work with since
proto boards were using A stepping processors. Everyone has
moved on. Therefore, drop non-proto support.
BUG=chrome-os-partner:56791
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16377
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Change-Id: I2985e3965b1b69445e22506bd664b4cbca13c8ab
Reviewed-on: https://chromium-review.googlesource.com/380997
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A pen interface was added. Prepare for possibly testing it by
plumbing in the gpio configuration. It's very possible these
changes need to be tweaked, but no driver code has been seen
yet nor a datasheet detailing how some of these signals actually
function.
BUG=chrome-os-partner:56739
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16376
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I208ff3e151ce55d62e5fcc33a1e39cc87e229970
Reviewed-on: https://chromium-review.googlesource.com/380996
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The formerly name FP_INT_L net is actually active high and is push-pull.
Therefore adjust for the new net name, FP_INT, and polarity. The
pulldowns are there because the device is on another board that isn't
always available.
BUG=chrome-os-partner:56740
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16375
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I6706fd2c2bd164cf3b5f1457aef69f5675f2112d
Reviewed-on: https://chromium-review.googlesource.com/380995
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Certain LPDDR4 models have some HW issues that can be worked around
by turning off Periodic Retraining feature in the memory controller.
Add option to disable PR per SKU.
BUG=chrome-os-partner:55466
BRANCH=None
TEST=run RMT test, pass
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16320
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Change-Id: Ie7aa79586665f6d3a7edd854a9eef07e6a1b2ab8
Reviewed-on: https://chromium-review.googlesource.com/380981
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
