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UPSTREAM: mainboard/google/reef: Disable CLKREQ of unused PCIe root ports

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1. Removes PCIe blocker for S0ix.
2. Set the correct PCIe root port for wifi/bt on EVT.
3. Turn off CLKREQs of unused PCIe root ports to power gate the IP.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16557
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Iefd8869688d3a44b435dab9fc792275cd7f7e091
Reviewed-on: https://chromium-review.googlesource.com/384962
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Venkateswarlu Vinjamuri 2016-09-08 15:25:35 -07:00 • committed by chrome-bot
commit f2d03a461a
1 changed files with 8 additions and 1 deletions
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9
src/mainboard/google/reef/variants/baseboard/devicetree.cb
View file

@ -4,7 +4,14 @@ chip soc/intel/apollolake
device lapic 0 on end
end
register "pcie_rp4_clkreq_pin" = "0" # wifi/bt
register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
# Disable unused clkreq of PCIe root ports
register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
# EMMC TX DATA Delay 1
# Refer to EDS-Vol2-22.3.