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UPSTREAM: mainboard/google/reef: Enable audio clock and power gate

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Removes S0ix blocker. Sets audio clock gate and power gate
bits when audio not in use. Reduces power in S0.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16424
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Id5c0adc2605480583dc90ee62a706dbfa4027c1b
Reviewed-on: https://chromium-review.googlesource.com/382082
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Venkateswarlu Vinjamuri 2016-09-02 16:07:08 -07:00 • committed by chrome-bot
commit effebd18ff
1 changed files with 5 additions and 0 deletions
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5
src/mainboard/google/reef/devicetree.cb
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@ -38,6 +38,11 @@ chip soc/intel/apollolake
# Enable DPTF
register "dptf_enable" = "1"
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"
register "hdaudio_pwr_gate_enable" = "1"
register "hdaudio_bios_config_lockdown" = "1"
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route, i.e., if this route changes then the affected GPE