Implement logo bitmap rotation within fsp_convert_bmp_to_gop_blt() to
support devices with portrait-oriented displays. The rotation is driven
by the panel framebuffer orientation, allowing the logo to be displayed
correctly regardless of physical panel orientation.
This resolves issues where the logo was displayed incorrectly on
portrait-oriented displays.
Additionally, discard the display orientation change if the LID is
closed aka built-in display is not active. This will ensure that
display orientation is proper when extended display is attached w/o
any display rotation.
BUG=b:396580135
TEST=Verified BMP logo display in landscape mode on a portrait panel
with rotation enabled. Also verified portrait logo display in landscape
mode with rotation enabled.
Change-Id: I110bd67331f01e523c227e1a4bdb0484f0157a60
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86850
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Taken from an ACPI dump from a Windows JSL device with MIPI camera.
Change-Id: Ibdb2b148ebfa85c3d4f5af2594b9b8847215e726
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This patch corrects spacing around assignment operators in the
`fill_blt_buffer` to comply with coding style guidelines, specifically
within the BMP color translation logic for 1/4/8/24/32-bit images.
Change-Id: Ia243d11568ec4c3d1108ff60289743919394aa32
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86860
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces a driver for the Intel Touch Controller (THC),
which supports HID-over-I2C and HID-over-SPI protocols, as well as
touch devices. The driver generates ACPI objects and publishes data
into the Secondary System Descriptor Table (SSDT) to facilitate
interaction with the touch hardware.
The driver implementation covers the following ACPI objects:
- _DSM (Device Specific Method)
- _CRS (Current Resource Settings)
- _STA (Power resource with Status), including _ON and _OFF methods
- _DSD (Device Specific Data) for THC-I2C
- _RST (Device Reset) for THC-SPI
Template device configuration for the following supported devices:
- Wacom: SPI touchscreen only
- Elan: both SPI and I2C touchscreen
- Hynitron: I2C touchpad only
It also includes template configurations for supported devices such as
Wacom (SPI touchscreen), Elan (SPI and I2C touchscreen), and Hynitron
(I2C touchpad). These configurations are divided into device-specific,
SoC-specific, and motherboard (MB)-specific details.
For SoC-specific configuration, the driver implements functions like
`soc_get_thc_hidi2c_info` and `soc_get_thc_hidspi_info`, which should
be defined in the SoC's `chip.c` file. Device-specific configurations
are provided by the driver for supported devices. For unsupported or
generic devices, the required information is expected to be provided
via the device tree. MB-specific information, such as LTR (Latency
Tolerance Reporting) values and speed, must be provided in the device
tree.
BUG=none
TEST=Configure the DRIVERS_INTEL_TOUCH option on a motherboard that has
the necessary touch configurations. Verify that the THC ACPI tables are
correctly generated in the SSDT.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Ibcd2a75a41460dee67aebdc61ee9e85fa98b71bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop duplicate/unused `mclk` field, which corrects the size of the SSDB
struct to 108 bytes. Size/fields confirmed by comparing to DSDT
dumps of UEFI firmware and SSDB struct in linux MIPI driver (ref:
/include/media/ipu-bridge.h).
Change-Id: Iea5b2138d2396e32bcecb3a48ab2b159a9b33345
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add more platform type values. Values sourced from Slimbootloader and
various DSDT dumps on github.
Change-Id: If7ea46aad76dfedf89f764e60d9bf6061f53cbe1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86794
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The _STA method of drivers/i2c/generic PowerResource currently always
returns true. To allow generating _STA that returns the device's actual
power state, this CL adds a new boolean option `use_gpio_for_status` to
the `drivers_i2c_generic_config` struct, and propagates the value to
`acpi_power_res_params` to reuse the feature implemented for acpi/device
in [1].
[1] https://review.coreboot.org/c/coreboot/+/55027
BUG=b:397355818
TEST=Dump SSDT on redrix with CB:86749
Change-Id: I5c0a423730788d634a780d1d1d8c87a7007cc150
Signed-off-by: Momoko Hattori <momohatt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sam McNally <sammc@google.com>
This patch moves the debug print which prints the mapping between CPU
Type-C port and EC Type-C port from SoC code to generic driver code.
BUG=b:399032094
TEST=Check the Type-C port and EC port mapping in coreboot log
Change-Id: Iaef5813cc825569a53feba975258f7d5fadecfab
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86704
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch adds the parameter which allows for custom port mapping
between CPU Type-C port and EC Type-C port to accommodate the
non-sequential mapping. Mainboard code must configure this parameter
if the CPU Type-C port to EC Type-C port mapping is not sequential.
BUG=b:399032094
TEST=build and verify TCSS port and EC port mapping
Change-Id: Id92f942e5c6b27342777b3e6fd12aff264ccec1b
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch refactors low-battery user notification logic (Kconfig,
APIs to check if low-battery rendering is required, low-battery
shutdown is required) outside FSP driver code to ensure in future
non-FSP platforms might still be able to leverage this feature/logics
to render the low-battery indicator icon during boot.
Specifically, it:
- Moves Kconfig options related to low-battery notifications from
drivers/intel/fsp to lib/
- Relocates the low-battery check and shutdown APIs drivers/intel/fsp
to bootsplash.h
* Adjusts the vendor driver to utilize the new APIs for low-battery
rendering decisions.
* Drop the unwanted header file "fsp/api.h" from bmp_logo.c
This change avoids tight coupling of low-battery functionality to FSP,
promoting code reusability across platforms.
BUG=b:400738815
TEST=Able to build and boot google/brox.
Change-Id: Iaa730dac2bb4866183408b6390221f0bb8411a48
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit relocates the BMP_LOGO related Kconfig options from the
FSP1.1 and FSP2.0 drivers to the common library (lib/).
This change:
- Centralizes the BMP_LOGO configuration, making it accessible to
all drivers and platforms.
- Removes duplicate Kconfig entries from the FSP drivers.
- Prepares for future refactoring where BMP_LOGO will be handled
entirely within the library, enabling its use by both FSP and
non-FSP platforms.
The following Kconfig options are moved under "Boot Logo Configuration"
menu option:
- `BMP_LOGO`
- `BMP_LOGO_COMPRESS_LZMA`
- `BMP_LOGO_COMPRESS_LZ4`
- `BMP_LOGO_FILE_NAME`
- `HAVE_BMP_LOGO_COMPRESS_LZMA`
- `HAVE_CUSTOM_BMP_LOGO`
BUG=b:400738815
TEST=Able to build and boot google/brox.
Change-Id: I9bbfade9b919cfbd0b689a67c988ed8c65deb597
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86730
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit standardizes the Kconfig option for the boot logo file name
across FSP drivers and the common library.
The `FSP1_1_LOGO_FILE_NAME` and `FSP2_0_LOGO_FILE_NAME` options are
renamed to `BMP_LOGO_FILE_NAME`.
BUG=b:400738815
TEST=Able to build and boot google/brox.
Change-Id: I6a6c2c6d235ad9643879b00232930c8a0d2e3801
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This change eliminates the HAVE_FSP_LOGO_SUPPORT Kconfig option.
It was initially used to control BMP_LOGO selection within the FSP2.0
driver. However, upcoming refactoring will move BMP_LOGO and its
implementation to the `lib` directory therefore, BMP_LOGO can be
used by both FSP and non-FSP SoC platforms.
BUG=b:400738815
TEST=Able to build and boot google/brox.
Change-Id: I899bbfcf7e747abe69ff0866c4594a42278891b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86719
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
As mentioned in comments on CB:83422, size of the current data
block (which is also the last block of a capsule) was incorrectly used
in place of the capsule size:
- when publishing a capsule in CBMEM (this worked in practice because
CapsuleApp.efi allocates a continuous physical memory)
- when aligning target address (which could move output pointer past
previously allocated buffer by up to 7 bytes per capsule block)
Change-Id: I97a528e2611fcd711c555d0f01e9aadcd2031217
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84542
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As was pointed out in comments on CB:83422 [0], the code lacks overflow
checks:
- when computing size of capsules in a single capsule block
- when computing size of capsules in all capsule blocks
If an overflow is triggered, the code might allocate a capsule buffer
smaller than the data that's going to be written to it leading to
overwriting memory after the buffer.
[0]: https://review.coreboot.org/c/coreboot/+/83422
Change-Id: I43d17d77197fc2cbd721d47941101551603c352a
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84541
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add PS0 and PS3 methods that return the Bluetooth power
resource. This allows the OS to turn on or off the device.
This fixes and issue where the Bluetooth reported a power
failure in device manager.
Change-Id: I0e37fc0369b1dc2b166f851daa183b145a09eb32
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86507
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
_PR3 should return resources required for the device to be in D3Hot
for which the Intel Bluetooth needs none, so remove it.
Change-Id: I65f206899affd46d791c2ba39235a1af320395d2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86595
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Don't attempt any GPIO operations of there isn't a reset
GPIO specified.
Change-Id: I9c97963e61f790f2d9c55d8ec1a384a5779782b4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86401
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Whilst the GPIO's used for Intel Bluetooth should always be consistent
as to whether they're active high or active low, adjust the driver to
pass the GPIO as a pointer, so that it can correctly account for
polarity.
Change-Id: Ib481d49d536b702fef149af882209501c61de6da
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add two new methods, CNVS and CNVC, that can check and control
the enable GPIO for a CNVi module.
These will be used by the common code for WiFi SW RF Kill (Low
Power Mode).
Change-Id: I09d0011ede6f739511a61daf2f1b317f6500a343
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit introduces an early low-battery shutdown mechanism during
FSP memory initialization. This is particularly important during
firmware updates, where memory training can consume significant power
and lead to abrupt shutdowns, potentially corrupting the firmware.
The changes include:
- Adding platform_display_early_shutdown_notification() to notify the
user of the impending shutdown.
- Checking platform_is_low_battery_shutdown_needed() to determine if a
shutdown is necessary.
- Implementing a shutdown sequence if low battery is detected during
memory init, especially when no MRC cache is found (i.e. firmware
update).
- Deferring shutdown on systems without MAINBOARD_HAS_EARLY_LIBGFXINIT
so that FSP-M (uGOP) can display a message.
This prevents firmware update corruption due to low battery.
BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.
Change-Id: Ia135b238d1e16722c2ca8d3b461e83b4ce513adf
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86452
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Commit `fb2c09d516` stopped the SSDT
containing TPM tables if PTT was not active, as at the time, the
table unconditionally reported the device present in the _STA
method.
Commit `d503ce1277` made the _STA to
return an accurate state, so now, the tables can always be
generated and Linux will report the presence correctly.
Change-Id: I594bf25a207b809c1ae2632eb1aea0d0fb6df35e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Refactor the vendorcode openSIL memory map code and move all common
calls that do not require any openSIL headers to the driver. Improve
the legibility of the logic to return memory hole type string.
Change-Id: I80b9bdd7fd633c7b12d695ced5d4b9b518570d80
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This method calls STXS and CTXS, which are both serialized so this
method itself does not need to be serialized.
Change-Id: I6d9d6d3b765bba918c08f64458bd1fdad18eff18
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86505
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This method calls STXS and CTXS, which are both serialized so this
method itself does not need to be serialized.
Change-Id: Ia46eaa8746bcff5a57831c14a2845139116b01da
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
This method only returns a package, so it does not need to be
serialized.
Change-Id: I5e61e92b0cffb28aaa070db3e9e8e2ff0e7c4251
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86503
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The scope should be closed with `acpigen_write_scope_end`, rather
than `acpigen_pop_len`.
Change-Id: I80df2ee1b51d7dbba85e556bee0fd7513ac933bb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86500
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds the `platform_is_low_battery_shutdown_needed` callback
to the FSP API. This allows platforms to integrate low-battery handling
logic directly into the FSP silicon initialization process. By checking
for critical conditions (e.g., low battery) within this callback after
FSP silicon initialization, the platform can initiate a controlled
shutdown before proceeding with further boot stages, preventing abrupt
shutdowns later in the boot process.
BUG=b:339673254
TEST=Able to build and boot google/brox.
Change-Id: I2d6677d70dea3d24f5a19d70608fd21229a271a0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86226
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit adds low battery indicator bitmap into CBFS. This screen
is displayed when the system detects a critically low battery condition.
The screen displays a logo and can be configured with a custom path.
An option to display an early low battery indicator in text mode is also
included. This early indicator can defer the firmware update.
This feature is controlled by the PLATFORM_HAS_LOW_BATTERY_INDICATOR
Kconfig option.
BUG=b:339673254
TEST=Able to see low-battery user notification in text mode before
memory init. Verified low-battery boot event listed in the eventlog.
Change-Id: I711c53455639b449fe85903139bbc06cdab08d09
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit moves the logo.bmp inclusion logic from
`src/drivers/intel/fsp2_0/Makefile.mk` to `src/lib/Makefile.mk`.
This change centralizes the logo inclusion logic within the `lib`
directory, aligning it with the location of `bmp_logo.c` and making
it independent of the FSP 2.0 driver.
Change-Id: I16ed1cf29b839c25b6ea1c2f10faf3d99dd707c9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The QEMU Bochs display driver uses 0x1CF as its VBE DISPI data port, but
this is only present on x86. Instead, use the port at 0x1D0 [1] which is
available on both x86 and non-x86 architectures. The data port is also
calculated inline based on the VBE DISPI index port while reading and
writing, update those expressions as well.
[1] https://web.archive.org/web/20240404032816/https://www.qemu.org/docs/master/specs/standard-vga.html#io-ports-used
Change-Id: I899beb742d42c26f3e57023f05ff459094fce5f1
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82061
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement vbt_get() on AMD and return the VBIOS location. This allows
to drop the hardcoded addresses used in various places and return an
address in DRAM that is reserved for FSP use.
TEST: amd/birman+ still gets passed the correct VBIOS address.
Change-Id: I92d76fc4df88fbce792b9d7c912c6799617704a0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86299
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
The `.devices` line only had once space before the =, as the tab
boundary is directly after the s of devices. The lines above had once
space after the last tab, so the equal sign is closer to the left side.
As the whole file aligns the equal sign, replace the space by a tab, and
do *not* go the route of not aligning the equal signs.
Change-Id: Ic49dc56263cafce3cfe40bb3ed7036fa25300f9f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This commit adds support for minimum/maximum limit values as well as
step sizes for CFR number options. Additionally, add a new flag that
specifies the option should be displayed in hexadecimal notation instead
of decimal.
Change-Id: I2e70f1430fb1911f1ad974832f8abfe76f928ac3
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Implements a way for CFR options to depend on another option
being set to one or more specific values. This is achieved
by writing a list of values as a varbinary struct.
Change-Id: Iaf7965551490969052eb27c207fa524470d4dd6a
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85987
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a version field to the CFR root struct so parsers can check
compatibility when parsing structs.
Change-Id: Ifcb950f1bdedc0ab925f3841befb7e7001c0f7f4
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
MAILBOXES_DESKTOP is unused, and the IGD opregion spec makes no
distinction in the mailboxes supported between desktop and mobile
platforms. Rename MAILBOXES_MOBILE to IGD_MAILBOXES for consistency
with other mailbox variables and clean up the comment.
Change-Id: Ia06fe75702887aa6953bf17bd4bc14af4038bec5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86279
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IGD mailbox #2, Software SCI Interface, is not supported by coreboot
currently, as it requires supporting the Get BIOS Data (GBDA) and
System BIOS Callbacks (SBCB) interfaces. Since coreboot doesn't
support these, don't advertise mailbox #2 support.
This eliminates an error with the Linux display drivers:
"SWSCI request timed out"
TEST=build/boot Linux 6.9, Win11 on starlabs/starlite_adl
Change-Id: I8efcf9c5d384b6e0ce159d65cb1497c2e2e47f42
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86276
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Intel's reference implementation in Slimbootloader pads the area
allocated for the extended VBT to the nearest 512-byte boundary, which
strongly suggests that the Windows driver expects the same.
TEST=build/boot Linux 6.9, Win11 on starlabs/starlite_adl, verify
VBT read properly by OS.
Change-Id: Ib3784eea6eb929ffec9672fc123b833c11c057e8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86275
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Define the generic cbmem_top_chipset() in the driver code, which will
invoke a SoC-specific vendorcode openSIL call to retrieve the low
usable DRAM address.
Change-Id: Ibc79456b0429cdd3d8e3fa5c224799a05add8359
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Refactor to factor out and route ACPI calls through the openSIL driver
interface to separate main SoC code from vendorcode.
Change-Id: I9fa4f60164333ec7a268702fa3e94979a1b83594
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit relies on newly added Kconfig option,
USE_CBFS_FILE_OPTION_BACKEND, which allows controlling the FSP debug
log level using CBFS options (RAW binary files).
The default log-level is setup in coreboot while stitching the CBFS
option binaries depending upon the coreboot log-level.
Following files will be used to determine the log levels:
- fsp_pcd_debug_level: For the overall FSP debug log level.
- fsp_mrc_debug_level: For the MRC (Memory Reference Code) debug log
level.
In absense of these files, the FSP console log-level is determine by
calling into fsp_map_console_log_level API.
The values in these files should correspond to the FSP_LOG_LEVEL_* enum
values.
This change allows for more flexibility in controlling the FSP debug log
level, especially in cases of debugging silicon firmware issues with a
debug AP FW binary.
This capability is particularly useful when debugging issues that
require examining both silicon and MRC logs simultaneously.
BUG=b:227151510
TEST=Able to control the FSP debug log based on CBFS options
To inject the fsp_pcd_debug_level and fsp_mrc_debug_level CBFS files
with the desired log level, run:
```
cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_pcd_debug_level
cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_mrc_debug_level
```
With both fsp_pcd_debug_level and fsp_mrc_debug_level present in the RO
CBFS, both the silicon firmware and MRC behave as debug binaries.
To verify the presence of both log-level RAW CBFS binaries in the CBFS RO
slot, run:
```
sudo cbfstool fatcat/image-rex0.serial.bin print | grep fsp_
```
This should output:
```
option/fsp_mrc_debug_level 0x88e40 raw 8 none
option/fsp_pcd_debug_level 0x2a7400 raw 8 none
```
Change-Id: I2c14d26021dd0048fa24024119df857e216f18bd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86001
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Some keyboard controllers need to have a specific bit in the command
byte set (e.g. PC_KBC_TRANSLATE) in order for the keyboard to function
properly.
Change-Id: I8745d1848f223634043eecc4659021a76a2b239b
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85330
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The fw_cfg device can be used by other qemu boards outside i440fx (and
q35, which manually includes the code). Factor out the fw_cfg code as a
separate driver that qemu mainboards can enable.
Change-Id: I8c5c4cb5f5478abd21aab8e8d0b503db41d81d40
Signed-off-by: Carlos López <carlos.lopez@openchip.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85673
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new option backend that uses values stored in CBFS files, similar
to the SeaBIOS runtime config options stored in files with the etc/
prefix. Options should be stored in CBFS with the option/ prefix. Values
can be set using `cbfstool coreboot.rom add-int -n option/<option-name>
-i <value>`. For simplicity, options should be stored in the COREBOOT
(RO) FMAP region, which is the default for cbfstool. This backend is not
available in SMM due to CBFS dependencies on vboot functions which are
not added to SMM, and thus the fallback will be returned by calls to
get_uint_option() in SMM.
Tested with QEMU Q35 by setting various options for "sata_mode" and
observing the console output for the SATA controller mode during
i82801ix_sata initialization.
Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The ASMedia ASM1061 seems to default to IDE mode, which seems to be the
source of payloads and Linux not recognizing/booting from drives
connected to it. From the behaviour of vendor firmware on the ASRock Z87
Extreme 4, the mode can be changed by setting the PCI Subclass register
to either 0x06 (SATA controller) or 0x01 (IDE controller). This register
seems to be read only, but can be unlocked for writing by setting bit 2
at offset 0xEC in the PCI config space.
Since the ASMEDIA_ASPM_BLACKLIST driver already existed and only matched
the ASM1061, rename it to ASMEDIA_ASM1061 and add the AHCI mode setting
code to it. To maintain consistency with chipset SATA ports, this is
also configurable through the existing sata_mode CMOS option with the
default set to AHCI.
Tested on the ASUS Maximus VI Gene.
Change-Id: I7a1470894261c7d14fadccdcade968f87f78fe23
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-by: Jan Philipp Groß <jeangrande@mailbox.org>
This resolves a crash issue observed on Meteor Lake and introduced by
commit 70bdd2e1fa ("cpu/x86/topology:
Simplify CPU topology initialization"). This commit simplifies the
code and provides more detailed CPU topology information by
generalizing the use of the Extended Topology Enumeration Leaves
0x1f. As a result, the coreboot APIC core_id field does not provide
the fully detailed path information.
It turns out that the topology core identifier is used by the coreboot
MP service mp_get_processor_info() implementation. But the MP Service
EFI_CPU_PHYSICAL_LOCATION data structure only captures information
about the package, core, and thread. The core identifier returned to
the MP service caller must incorporate the full hierarchical path (die
group, die, module, tile, module and core).
This commit adds a new field to the cpu topology structure to
represent the core ID within the package.
For reference, here is that signature of the crash:
LAPIC 0x40 in X2APIC mode.
CPU Index 2 - APIC 64 Unexpected Exception:13 @ 10:69f3d1e4 - Halting
Code: 0 eflags: 00010046 cr2: 00000000
eax: 00000001 ebx: 69f313e8 ecx: 0000004e edx: 00000000
edi: 69f38018 esi: 00000029 ebp: 69aeee0c esp: 69aeedc0
[...]
The crash occurred when FSP attempted to lock the Protected
Processor Inventory Number Enable Control MSR (IA32_PPIN_CTL
0x4e).
69f3d1d3: 8b 43 f4 mov -0xc(%ebx),%eax
69f3d1d6: 89 4d c4 mov %ecx,-0x3c(%ebp)
69f3d1d9: 89 45 dc mov %eax,-0x24(%ebp)
69f3d1dc: 8b 55 c4 mov -0x3c(%ebp),%edx
69f3d1df: 8b 45 c0 mov -0x40(%ebp),%eax
69f3d1e2: 8b 4d dc mov -0x24(%ebp),%ecx
69f3d1e5: 0f 30 wrmsr
69f3d1e7: e9 ee fd ff ff jmp 0xfffffe39
FSP experiences issues due to attempting to lock the same register
multiple times for a single core. This is caused by an inconsistency
in the processor information data structure, where multiple cores
share the same identifier. This is not permitted and triggers a
General Protection Fault Exception.
TEST=Executing CpuFeaturesPei.efi in FSP-S does not crash on a rex
board.
Change-Id: I06db580cddaeaf5c452fa72f131d37d10dbc5974
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86004
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Rather than unconditionally returning that the device is present,
return whether the fTPM is on or not.
Test=Boot the StarLite Mk V with the Intel ME disabled, and check
that the TPM is reported as not present.
Change-Id: If8236021bf0e1264646971cff9c998fac99ac220
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85228
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
