Add H58G56DK9BX068 in the memory_parts.json and re-generate the SPD.
BUG=none
TEST= Booted successfully on nvlrvp board using H58G56DK9BX068.
util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I7f8e13c2dac50b108f3ded1528a48b641eafbeec
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90856
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add MT62F2G32D4DS-031RFWT:C in the memory_parts.json and re-generate
the SPD.
Micron: MT62F2G32D4DS-031RFWT:C
BUG=b:447273470
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I2dc0151db31ed07c61454e800d539c9b546a1ea7
Signed-off-by: Zheng Li <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This patch adds three more parts that are used in Lenovo Thinkpads:
SKHynix H5AN4G6NAFR-UHC
SKHynix H5ANAG6NAMR-UHC
Micron MT40A512M16LY-075:H
The settings (MT/s, timing, organization, etc.) have been obtained from
schematics and datasheets.
Change-Id: Ie0958a4a845f072daee3379731f558584dca5da6
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This fixes an error I made in my previous commit 8a83b86254 (spd/ddr4:
add parts), CB:90032. The package bus width for all the dual die parts
is indeed 16 rather than 8. This has been validated when porting
coreboot to the Lenovo Thinkpad X280 that uses soldered-on DDP RAM
(Samsung K4AAG165WB-MCRC).
Change-Id: I8baa7c979074584e65772315e66e787cef3202e4
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add MT62F1G32D2DS-031RF WT:C in the memory_parts.json and re-generate
the SPD.
BUG=b:459934066
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: Ib65f24347ddae2808720f8e3c73652a82de94311
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90019
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds parts used on Lenovo Thinkpads:
Micron MT40A512M16HA-083E:A
Micron MT40A1G16HBA-083E:A
Samsung K4A8G165WB-BCPB
Micron MT40A512M16JY-083E:B
Micron MT40A1G16WBU-083E:B
Samsung K4A8G165WC-BCRC
Samsung K4AAG165WB-MCRC
SKHynix H5AN8G6NAFR-UHC
SKHynix H5AN8G6NAMR-UHC
Micron MT40A512M6LY-075:E
Micron MT40A256M16GE-083E
Samsung K4A4G165WE-BCRC
The SPD data (timing, configuration, etc.) has been extracted from datasheets and laptop schematics. When there has been conflicting data between these data sources, slower (safer) values were picked.
Change-Id: Ied92619130feaa160d01f75bc38230ab6a024ace
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90032
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add H58GE6AK8BX104 in the memory_parts.json and re-generate
the SPD.
BUG=b:445211686
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I4bf1d0fc3325ec2d4247a0263a44a81934a3a90e
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add MT62F1G32D2DS-031 WT:C and MT62F2G32D4DS-031 WT:C in the
memory_parts.json and re-generate the SPD.
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I0db533908fbea2bc04a55191960aaeec8461f47d
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Add MT62F2G32D4DS-023 WT:C in the memory_parts.json and re-generate the
SPD.
BUG=b:427327667
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I8f244c2f91d66ffcbc1ec2642304f77b522da09f
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
According to the latest SPD parameters provided by the manufacturer,
combined with the document 8Gb_LPDDR4X_B_Die_component_Datasheet(S).pdf
we correct channelsPerDie, diesPerPackage, ranksPerChannel of SPD
for Nanya NT6AP1024F32BL-J1; merged the parameters into the BIOS and
flashed it into the machine. The machine can boot and read the normal
size of memory.
BUG=b.422906387
TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x
Use the dmidecode -t memory command to read the size of memory.
Output results：
awasuki-rev2 # dmidecode -t memory
# dmidecode 3.4
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x000A, DMI type 16, 23 bytes
Physical Memory Array
Location: System Board Or Motherboard
Use: System Memory
Error Correction Type: None
Maximum Capacity: 64 GB
Error Information Handle: Not Provided
Number Of Devices: 4
Handle 0x000B, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000A
Error Information Handle: Not Provided
Total Width: 32 bits
Data Width: 32 bits
Size: 8 GB
Form Factor: Unknown
Set: None
Locator: Channel-0-DIMM-0
Bank Locator: BANK 0
Type: LPDDR4
Type Detail: Synchronous
Speed: 2933 MT/s
Manufacturer: Unknown (b03)
Serial Number: 00000000
Asset Tag: Not Specified
Part Number: NT6AP1024F32BL-J1
Rank: 2
Configured Memory Speed: 2933 MT/s
Minimum Voltage: 0.6 V
Maximum Voltage: 0.6 V
Configured Voltage: 0.6 V
Change-Id: I35823ce87b5d8d67894528e4a8781dd91247eb6c
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88146
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add K3KL9L90EM-MGCU in the memory_parts.json and re-generate the SPD
Samsung:K3KL9L90EM-MGCU
BUG=b:416632273
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I693d52714a3d1846dec1f990ba7d9f23ec5f219f
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Add Micron memory part H58G56CK8BX146 to LP5 global list.
And Regenerate the SPD files for the SoC. The specification
is attached in issue tracker.
BUG=b:367841051
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I2a003aad32bca9ae5438973ecf0d7872481fee20
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch add support for PTL platform to the `spd_tools`.
This would be useful to create dynamic SPD for fatcat variants.
BUG=b:347669091
TEST=Able to generate SPD for LP5 DRAM part.
Change-Id: I55c3f49439fb1ad961c6866f03594431e54279b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83822
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
This adds support for Zilia SDVB8D8A34XGCL3N3T LP4x chips.
Generatd SPD data with:
util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x
BRANCH=None
BUG=344482259
Change-Id: I4408e62ab2a15002960c1d9659ab6af45bd7f7bb
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add MT62F1G32D2DS-023 WT:C and K3KL8L80DM-MGCU
in the memory_parts.json and re-generate the SPD
Micron:MT62F1G32D2DS-023 WT:C
Samsung:K3KL8L80DM-MGCU
BUG=b:337730271
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: Ic5c3ed46829330f83e144cf8d18be6fa808431aa
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Update spd_gen and part_id_gen utilities to accommodate Phoenix platform
so that SPD can be generated for the memory parts used in that platform.
SPD requirements for Phoenix and Mendocino platforms are identical.
BUG=b:273383819
TEST=Run spd_gen and ensure that both Mendocino and Phoenix platforms
share the platform manifest for LP5 memory parts.
Change-Id: I7a12f73065864f08db8922c1a69eb503865a25b1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Add Micron memory part MT62F1G32D2DS-023 and MT62F2G32D4DS-023 to LP5
global list. Attributes are derived from CCM005-1974498342-145. Also,
regenerate the SPD files for the SoC.
BUG=b:271188237
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I6675a68b7a515bd6d21db3ea2da762b06dee017a
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Because SPD tool now supports 8533Mbps, so modify speed to regenerate
the SPD file for Hynix H58G66BK8BX067 and H58G56BK8BX068.
BUG=b:263189532, b:270629852
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I813fc1495836dbe33de426cf41a1f58c8e8a046e
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73251
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Chao Gui <chaogui@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
HYNIX H58G56BK8BX068 will be used for omnigul.
Add it to the parts list and regenerate the SPDs using spd_gen.
BUG=b:264340545
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: Id4adbaf7611e34107522df988482d9efd229d514
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72967
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Micron H58G66BK8BX067 will be used for omnigul.
Add it to the parts list and regenerate the SPDs using spd_gen.
BUG=b:264340545
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: Ida422b17d7abfd130a80a28e49a1fa1b70043adf
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72885
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Correct Hynix ddr4 part number H5AG36EXNDX019 to H5AG36EXNDX017 by Hynix Memory spec.
BUG=b:236739240
BRANCH=Volteer
TEST="util/spd_tools/bin/spd_gen memory_parts.json ddr4" and verify it builds successfully.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: I6195fa1402691afc303f5223de48f552660cd97f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71159
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update bitWidthPerChannel in memory_parts.json and re-generate the SPD.
Then the device boots successfully with DDR H9JCNNNFA5MLYR-N6E.
BUG=b:261530632
BRANCH=None
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: Ib78c2e28394206b59c41b6b28cf24d8a756f7ae9
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Mendocino supports LP5x but currently doesn't support SPDs that use the
LP5x memory type, 0x15. This commit updates set 1 SPDs, which are
currently only used for mendocino, to use 0x13 for their memory type.
BUG=b:245509394
TEST=Generated SPDs, verified that only set 1 have changed to 0x13
Change-Id: I46606cb5ff871296d0214e1f781c3b22e93d24ea
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67747
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This updates the SPD utility and generated SPDs for LP5X to use memory
type code 0x15 (LPDDR5X) instead of 0x13 (LPDDR5). This is done based on
Intel Tech Advisory Doc ID #616599 dated May 2022, page 15.
SPDs were regenerated with:
"util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5"
This only affects the SPDs for 2 memory parts for Intel SoCs and the
only board referencing these is rex.
BUG=b:242765117
TEST=inspected SPD hex dump
Change-Id: Iadb4688f1cb4265dab1dc7c242f0c301d5498b83
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This commit adds support for LP5X SPDs. The SPD format is identical to
LP5 except that the memory type is set to 0x15 instead of 0x13. Since
they are essentially the same, LP5/5X parts share the same parts JSON
file and SPD directory. LP5X parts are distinguished by the optional
`lp5x` attribute. This commit also updates two existing LP5X memory
parts with the correct attribute.
BUG=b:242765117
TEST=Generated SPDs, verified that SPDs generated from LP5X parts match
their LP5 counterparts except for memory type byte.
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I67df22bc3fd8ea45fe4dad16b8579351eb4d0d8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Firmware component that does memory training already limits the memory
controller to train at 5500 Mbps for all memory parts in Sabrina. Hence
removing this interim SPD change to limit the speed.
BUG=b:238074863
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I2bc82c7407a97aac282708c3e0bd56ae99a8fc31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66290
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
