Johann C. Rode e4a809d441 spd/ddr4: Double packageBusWidth of dual die package parts to 16 ... This fixes an error I made in my previous commit 8a83b86254 (spd/ddr4: add parts), CB:90032. The package bus width for all the dual die parts is indeed 16 rather than 8. This has been validated when porting coreboot to the Lenovo Thinkpad X280 that uses soldered-on DDP RAM (Samsung K4AAG165WB-MCRC). Change-Id: I8baa7c979074584e65772315e66e787cef3202e4 Signed-off-by: Johann C. Rode <jcrode@gmx.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>		2025-12-02 01:54:18 +00:00
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ddr4	spd/ddr4: Double packageBusWidth of dual die package parts to 16	2025-12-02 01:54:18 +00:00
lp4x	spd/lp4x: Add CXMT CXDB5CBAM-MA-B memory	2025-11-06 16:28:14 +00:00
lp5	spd/lp5: Add SPD for MT62F1G32D2DS-031RF WT:C	2025-11-29 20:03:21 +00:00