Limit the ACPI OpRegion to cover only MBOX3. This seems to fix
BSOD errors seen on Windows 10/11 as reported at [1].
1: https://ticket.coreboot.org/issues/327
Change-Id: Ia2affa799e5cd84c0a03330e0f78919755f0e8ac
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81295
Reviewed-by: Joel Linn <jl_coreboot@conductive.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Fill 'rpmc_caps' struct inside the 'spi_flash' struct with the RPMC info
from the SFDP table.
TEST=On a board with a W74M12JW SPI flash chip, the 'rpmc_caps' struct
has the expected entries (RPMC available, OP2 extended status as polling
method, 4 RPMC counters, OP1 is 0x9b, and OP2 is 0x96).
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a8332bffe93e1691f6fc87c3936025f158f3ab9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
JESD216F.02 and JESD260 were used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a1f7a5d16dd3ca6c8263b617ae9c21184b6a5b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85008
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add basic support for the Serial Flash Discoverable Parameters (SFDP)
standard which can be used to discover the parameters to interact with
any SPI flash chip that supports this mechanism. This commit adds
functionality to find specific SFDP parameter headers and print all SFDP
parameter headers, but not to parse any SFDP parameter table. This is a
preparation for a follow-up patch that adds support to parse the RPMC
SFDP parameter table. Since 'find_sfdp_parameter_header' is only used in
the next patch, it's marked as static inline in this commit so that the
code still build; the 'inline' keyword will be removed again in that
follow-up patch.
For now, only the legacy access protocol using single bit SPI transfers
is supported, but this should cover most of the SPI NOR flash chips. In
any other case, the code will error out. It's also assumed that the SFDP
data blocks read from the SPI flash chip are small enough to fit into
the SPI host controller buffer and don't need to be broken up into
multiple transfers. This limitation will be addressed in a follow-up
patch.
JESD216F.02 was used as a reference.
TEST=On a board with a W74M12JW SPI flash chip, calling
'spi_flash_print_sfdp_headers' prints this on the console output:
Manufacturer: ef
SF: Detected ef 6018 with sector size 0x1000, total 0x1000000
SF: Exiting 4-byte addressing mode
SFDP header found in SPI flash.
major rev 0x1, minor rev 0x6, access protocol 0xff, number of headers 3
SFPD header with index 0:
table ID 0xff00, major rev 0x1, minor rev 0x6
table pointer 0x80, table length DWORDS 0x10
SFPD header with index 1:
table ID 0xff84, major rev 0x1, minor rev 0x0
table pointer 0xd0, table length DWORDS 0x2
SFPD header with index 2:
table ID 0xff03, major rev 0x1, minor rev 0x0
table pointer 0xf0, table length DWORDS 0x2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5a1706acf7d60fd64292e8f0677992ab4aebf46a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
A following patch that adds some support for reading the serial flash
discoverable parameters (SFDP) data structures needs to send more than
just the one command byte that 'spi_flash_cmd' supports. To be able to
do this, introduce the 'spi_flash_cmd_multi' function which supports
sending multiple bytes before reading back some bytes. The prototype is
added to drivers/spi/spi_flash_internal.h since only other files in the
same directory are supposed to be using that function.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1f3872463249240c0a32e2825e4302894e856b2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84789
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This to fix the error when using C23:
cannot cast an object of type 'nullptr_t' to 'uintptr_t' (aka 'unsigned long')
return (uintptr_t)NULL;
^
Change-Id: Ibdc8794513a508fc61a5046692f854183c36b781
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Adjust the DSM to return 0x00 (unsupported) when no reset gpio
is passed to the driver. Leave the _RST method to comply with
the ACPI specification but omit the BTRT method as it won't do
anything.
Change-Id: I9f8e98fb4f5a22b2f7617b131a3d71cf90f5bc80
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
The current panel brightness is only 360 nits. Adjust the power and
gamma to optimize the panel brightness. The brightness after adjustment
is 390 nits.
BUG=b:320892589
TEST=boot ciri with IVO_T109NW41 panel and see firmware screen
BRANCH=geralt
Change-Id: I760c37bf915bb40ad2efa7c947034cb168938f2a
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84758
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Linux has never supported this feature, and according to our FAE, the
Windows driver dropped support for it in 2022 so remove it.
Change-Id: I4f0b6108bb5db657490a8b9395bb99378fc63c4d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Add support for RTD3 for Intel Bluetooth. This is done by
controlling the enable GPIO (GPP_VGPIO_0 for most SOCs) that
exists on all wireless cards since Jefferson Peak.
The exception is GalePeak2, which uses VSEC and this driver doesn't
support that.
Change-Id: Ibea97ab0ae0a9f1eb6aaca43d831bb4ce7bdc02e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Add AOLD Method, which returns an integer based on
whether Audio Offload is enabled. Leave the existing
control of Audio Offload in `soc/soc_chip.h`. Add
`cnvi_bt_audio_offload` in the USB ACPI `chip.h` to
control the aforementioned return value.
The value in `soc/soc_chip.h` and `chip.h` should
match.
Change-Id: Idb804fb1cf0edef4a98479a6261ca68255dbf075
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84134
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TPM_RDRESP_NEED_DELAY was introduced in 2018 in CB:25322 after
observing errors with SLB9635 by Infineon. It has been confirmed
also SLB9670 and SLB9672 require a fix or delay here.
Presumably, prior to CB:4388 SLB9635 did not have this problem,
as this particular TPM shipped with samsung/lumpy Chromebook since
2011. In CB:4388 the code changed from polling the status register
(+burst_count) using a 32bit read to separated 8bit reads.
So far, experiments on samsung/lumpy and SLB9635 indicate that
it would be sufficient to add a single tpm_read_status() call
to see TIS_STS_DATA_AVAILABLE as set at the time of evaluating
the loop exit condition.
Change-Id: If5c3e93c7946ebf8226f7bba47b38253f6920c61
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Co-authored-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
STMicro first moved their SPI NOR flash business to Numonyx which was a
joint venture with Intel which later got sold to Micron, so add a
comment to the VENDOR_ID_STMICRO JEDEC manufacturer ID define and
mention all 3 companies that have sold SPI NOR flash chips using this
manufacturer ID to the Kconfig help text of SPI_FLASH_STMICRO.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7886396d8f0a9766f568a221c0b5ade02489060b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84018
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Since version 6.6, Linux has warned about the lack of a
_PRR Method being available for Intel Bluetooth. Add one
that follows the recommendations from Intel in their
connectivity integrated guide, that uses the reset
delay set by the DSM.
Change-Id: I9c7fd286e8630d77d79d1d7cd113ce3a3d3d0fe3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84145
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Intel Bluetooth driver can be combined with either CNVi, or
full PCI wireless cards such as the AX210. Move it to the USB
code so it can be used by either or.
Change-Id: Ib456b1870501182b2d8788e5d53bbf4d7981f91b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84627
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The code for Intel Bluetooth is unrelated to all other devices, and
needs to grow in size - move it to another file.
Change-Id: I65ccb9f2fd95b07fa63866485920539adc474873
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84625
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change updates SoundWire driver to support ALC721 audio codec
based on config flag.
reference datasheet: Realtek ALC721-VA0-CG Rev. 0.34
BUG=b:368495490
TEST=This driver was tested on Intel RVP with Add-on ALC721 codec card
by testing soundcard binding/devices are detected and check for audio
playback.
Change-Id: I1022ee91b16374d0d4d07e5198226595d61403a6
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Signed-off-by: Naveen M <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This change removes individual conditional blocks for specific ALC
codec models and introduces a common name for the entire ALC 7 Series
configuration.
TEST=Build and test with DRIVERS_SOUNDWIRE_ALC_BASE_7XX.
Change-Id: Ib7c33351207df472cd11243244063b007c24d9bf
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The method "FUNC" allows 1 argument, so remove the
incorrectly referenced and unused second arguemnt.
This fixes:
ToInteger (Arg1, Local1)
Error 6006 - ^ Method argument is not initialized (Arg1)
Change-Id: If5e402579a2caff169e12253e5d9c2c493902ec7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
This change removes the SoC-specific `FSP_STATUS_GLOBAL_RESET_REQUIRED_X`
Kconfigs, as they are no longer necessary for handling FSP global reset
requests.
Previously, these Kconfigs were used to select a specific 32-bit reset
status code. However, with the introduction of FSP 2.4 and 64-bit
interfaces, the global reset status code can now vary between
architectures.
To address this, the FSP driver now sets the `FSP_STATUS_GLOBAL_RESET`
config to a common default value (depending upon most commonly used
global reset status code) based on the interface:
- 0x40000003 for 32-bit FSP interfaces
- 0x4000000000000003 for 64-bit FSP interfaces
This default can be overridden if an FSP implementation uses a
different status code (for example: Apollo Lake selects different FSP
reset status code as 0x40000005).
By removing the SoC-specific configurations, this change simplifies
global reset handling and ensures compatibility across different FSP
versions and platforms.
Below table shows the relationship between Platform, FSP and FSP Global
Reset Status:
+-----------------+--------------+-------------------------+
| Platform | FSP | Global Reset Status |
+-----------------+--------------+-------------------------+
| Alder Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Apollo Lake | 32-bit | 0x40000005 |
+-----------------+--------------+-------------------------+
| Cannon Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Elkhart Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Jasper Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Meteor Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Sky Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Tiger Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Panther Lake | 64-bit | 0x4000000000000003 |
+-----------------+--------------+-------------------------+
BUG=b:347669091
TEST=Verified FSP requested global reset functionality on google/rex0
(32-bit) and google/rex64 (64-bit) platforms.
w/ 32-bit FSP:
```
(Wdt) AllowKnownReset
[FspResetSystem2] FSP Reset Initiated
FSP returning control to Bootloader with reset required return status
40000003
FSPS, status=0x40000003
FSP: handling reset type, status=0x40000003
GLOBAL RESET!
global_reset() called!
HECI: Global Reset(Type:1) Command
```
w/ 64-bit FSP:
```
(Wdt) AllowKnownReset
[FspResetSystem2] FSP Reset Initiated
FSP returning control to Bootloader with reset required return status 3
FSPS, status=0x4000000000000003
FSP: handling reset type, status=0x4000000000000003
GLOBAL RESET!
global_reset() called!
HECI: Global Reset(Type:1) Command
```
Change-Id: I32bdbf7ea6afa7d5e5f91ea96d887719d26a593f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84572
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Add a Power Resource for Intel Bluetooth, that can reset
the Bluetooth using the delay configured in the DSM.
Change-Id: I3b25fd180e21100e3cb001fc6ba0da7f47b2ad12
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84146
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This should be the sane default, as having this option enabled when the
AT24RF08C (Asset Identification EEPROM) is not present on the mainboard
can cause SMBIOS table entries to become "*INVALID*". This can,
for example, result in strange hostnames when an OS installer uses
SMBIOS information to automatically generate one. On the other hand,
the coreboot generated SMBIOS tables will at least always contain basic
information. Therefore, this driver should be treated as an enhancement
rather than a default.
Currently, the following mainboards have this option disabled:
- ThinkCentre M710s
- ThinkCentre M700 / M900 Tiny
- Haswell ThinkPads
- ThinkPad T440p
- ThinkPad W541
Therefore, we can remove this option entirely on these mainboards. Note
that there may be other mainboards which do not have this chip present
but still have the option enabled. However, this requires a more
detailed investigation which would be out of scope of this change.
TESTS=Timeless builds on lenovo mainboards produce the same binary.
config INCLUDE_CONFIG_FILE
default n
Was temporarily added to `mb/lenovo/Kconfig` during these tests, as
while the configuration does not change, the order of entries do.
Therefore, technically producing a different binary when included.
Change-Id: I5bb101bd6696c39718ee779426d0ec3e721e1b51
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84544
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This allows to configure a default screen rotation in 90-degree
steps. The framebuffer contents will then be displayed rotated,
by the same amount in the other direction; i.e. if you turn the
screen to the left, the picture has to be rotated to the right
to accommodate.
This is only supported by libgfxinit from Skylake / Apollo Lake
on (earlier GPUs didn't support the 90-degree steps anyway) and
it only works with the linear-framebuffer option.
Change-Id: Iac75cefbd34f28c55ec20ee152fe67351cc48653
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit introduces a new config DRIVER_INTEL_ISH_HAS_MAIN_FW to
indicate that the Intel Sensor Hub (ISH) is using the ISH MAIN firmware.
The ISH MAIN firmware is located in rootfs, hence we no longer need to
store the ISH BUP version in the CSE partition.
When this config is enabled, fetching the ISH BUP version from the CSE
firmware partition is skipped.
BUG=b:360144613
TEST=Local build successful and tested on trulo by toggling the
config. Enabling this config skips printing the ISH version in cbmem.
Change-Id: I6cacf7b44ce6895ecb96db295d184c7b7d5a872c
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84493
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Add support for AST2600 as found on Intel Archer City CRB by using
the code found on Linux's ast drm driver.
While on it do minor modifications found on the Linux drm driver
that also affect the other ast chips.
New log messages:
[INFO ] ASpeed AST2050: initializing video device
[INFO ] ast_detect_chip: VGA not enabled on entry, requesting chip POST
[INFO ] ast_detect_config_mode: Using P2A bridge for configuration
[INFO ] ast_detect_chip: AST 2600 detected
[INFO ] ast_detect_chip: Analog VGA only
[INFO ] ast_driver_load: dram MCLK=890316000 MHz type=3 bus_width=16 size=01000000
[ERROR] No header found
[INFO ] ast_select_mode: Failed to decode EDID
[DEBUG] Assuming VGA for KVM
[DEBUG] AST: Display has 1024px x 768px
[DEBUG] Using framebuffer 1024px x 768px pitch 4096 @ 32 BPP
[INFO ] framebuffer_info: bytes_per_line: 4096, bits_per_pixel: 32
[INFO ] x_res x y_res: 1024 x 768, size: 3145728 at 0x94000000
[INFO ] ASpeed high resolution framebuffer initialized
TEST: Booted on Intel/ArcherCity CRB and used the UEFI firmware menu
over KVM using native graphics init.
Change-Id: I3d2d58d493706673c1b2ba4953967b1641bd6395
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Move the `BUILDING_WITH_DEBUG_FSP` Kconfig option from SoC-specific
files to the FSP2_0 driver Kconfig to avoid duplication. Also slightly
improves the option's prompt and help text.
TEST=Built and booted google/rex successfully.
Change-Id: I5c3dce59c396f6c1665a3ed1b8c1bb5df0f5a8d4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This patch adds a new Kconfig option `FSP_PUBLISH_MBP_HOB` to
control the creation of the ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP.
Disabling this option can improve boot time on platforms that
do not utilize the MBP HOB, such as ChromeOS devices.
The option is disabled by default on ChromeOS and enabled
by default on other platforms.
On ADL-P based platforms, this option is forced to be enabled
as ADL-P FSP relies on MBP HOB for ChipsetInit version for
ChipsetInit sync.
Removed SoC specific implementation of `FSP_PUBLISH_MBP_HOB` config
from MTL and TGL config file.
TEST=Tested on ADL-P and ADL-N platforms. Verified that MBP HOB is
created when `FSP_PUBLISH_MBP_HOB` is enabled and not created when
it is disabled.
Also verified that the system boots successfully in both cases.
Change-Id: I21da00259c0b9bcca6f545291a6259e9cce8d900
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
There are one too many acpigen_pop_len calls in the code
to generate the ROTM; remove one to fix an EMERG warning:
[EMERG] ASSERTION_ERROR: file `src/acpi/acpigen.c`, line 38
The extra acpigen_pop_len() call was added commit
45d2c3d543 ("i2c/drivers/generic: Return ROTM in a package").
Change-Id: I913022144813f7f65eac1bcb7c97656f2c513c0b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add support for creating a DSM Method for Intel Bluetooth that
is outlined in Intel's connectivity integrated guide (which has
no document number).
It supports two GUIDs:
Set Tile Activaction (2d19d3e1-5708-4696-bd5b-2c3dbae2d6a9)
BIT(0) Indicates whether the device supports other functions
BIT(1) Set Tile Activation
Check/Set Reset Delay (aa10f4e0-81ac-4233-abf6-3b2ac50e28d9)
BIT(0) Indicates whether the device supports other functions
BIT(1) Set Bluetooth reset timing
Change-Id: Icc18f867604876b27ced2ee4356e47b3aa6b4f74
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84133
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
How it approximately works:
(During a normal system run):
1. OS puts a capsule into RAM and calls UpdateCapsule() function of EFI
runtime
2. If applying the update requires a reboot, EFI implementation creates
a new CapsuleUpdateData* EFI variable pointing at the beginning of
capsules description (not data, but description of the data) and does
a warm reboot leaving capsule data and its description in RAM to be
picked by firmware on the next boot process
(After DEV_INIT:)
3. Capsules are discovered by checking for CapsuleUpdateData* variables
4. Capsule description in memory and capsule data is validated for
sanity
5. Capsule data is coalesced into a continuous piece of memory
(On BS_WRITE_TABLES via dasharo_add_capsules_to_bootmem() hook:)
6. Buffer with coalesced capsules is marked as reserved
(On BS_WRITE_TABLES via lb_uefi_capsules() hook:)
7. coreboot table entry is added for each of the discovered capsules
(In UEFI payload:)
8. CapsuleUpdateData* get removed
9. coreboot table is checked for any update capsules which are then
applied
Change-Id: I162d678ae5c504906084b59c1a8d8c26dadb9433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
The current region_end() implementation is susceptible to overflow
if the region is at the end of the addressable space. A common case
with the memory-mapped flash of x86 directly below the 32-bit limit.
Note: This patch also changes console output to inclusive limits.
IMO, to the better.
Change-Id: Ic4bd6eced638745b7e845504da74542e4220554a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch adds SoundWire driver to support ALC722 audio codec.
The existing ALC711 codec driver is refactored to include support for
ALC722 device based on config flag.
The ACPI address for the codec is calculated with the information in
the codec driver combined with the devicetree.cb hierarchy where the
link and unique IDs are extracted from the device path.
For example this device is connected to master link ID 0 and has strap
settings configuring it for unique ID 1:
chip drivers/soundwire/alc711
register "desc" = ""Headset Codec""
device generic 0.1 on end
end
reference datasheet: Realtek ALC722-CG ver. 0.56
TEST=This driver was tested on Intel RVP with on board ALC722 codec
by booting and disassembling the runtime SSDT to ensure that the
devices have the expected address and properties. Test soundcard
binding works and devices are detected and check for audio playback
using speaker output.
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ieb16a1c6f3a79321fdc35987468daa8be33b6e49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
EFI System Resource Table (ESRT) is an informational structure that
reports basic details about current system or device firmware. This is
chiefly used to perform firmware updates.
New CONFIG_DRIVERS_EFI_FW_INFO is off by default, enabling it adds
DRIVERS_EFI_FW_{GUID,VERSION,LSV} to be used to specify firmware
version/update information.
Existing forms of versions wouldn't be sufficient because there is no
universal way of converting string versions to 32-bit unsigned integers
and there are no GUIDs or lowest supported versions.
Change-Id: Ic1b768d7bed43edf7ca8e41552087734054de033
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83421
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both AGESA.h and cpu/amd/mtrr.h defined TOP_MEM and TOP_MEM2, but since
it was defined as unsigned long in AGESA.h, a workaround was needed in
cpu/amd/mtrr.h to not have the build fail due to a non-identical
redefinition of TOP_MEM and TOP_MEM2. Just removing the workaround
without reaming the defines isn't trivially possible, since the
stoneyridge romstage.c still ends up including both definitions which
can't be easily worked around. Now all non-vendorcode coreboot code uses
TOP_MEM_MSR and TOP_MEM2_MSR while the vendorcode part uses TOP_MEM and
TOP_MEM2 to avoid this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibad72dac17bd0b05734709d42c6802b7c8a87455
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This patch introduces a new configuration option,
FSP_UGOP_EARLY_SIGN_OF_LIFE, to the FSP driver. This enables uGOP
support using FSP-M for the early sign-of-life feature in SOC.
BUG=NA
TEST=Able to build google/rex and checked the config in output.
Change-Id: Ic0426ff7974a141ae9188b0098677b4cc97aee36
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
We introduce two new functions to create region objects. They allow us
to check for integer overflows (region_create_untrusted()) or assert
their absence (region_create()).
This fixes potential overflows in region_overlap() checks in SMI
handlers, where we would wrongfully report MMIO as *not* overlapping
SMRAM.
Also, two cases of strtol() in parse_region() (cbfstool), where the
results were implicitly converted to `size_t`, are replaced with the
unsigned strtoul().
FIT payload support is left out, as it doesn't use the region API
(only the struct).
Change-Id: I4ae3e6274c981c9ab4fb1263c2a72fa68ef1c32b
Ticket: https://ticket.coreboot.org/issues/522
Found-by: Vadim Zaliva <lord@digamma.ai>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
When both CRB and pc80 TPM drivers are compiled in, building fails
because the tpm_config_t typedef has two incompatible definitions.
Given that typedefs are discouraged by the project's coding style,
simply get rid of the tpm_config_t typedef.
TEST=Compile MSI PRO Z690-A target with CRB and PC80 TPM chips enabled
in devicetree.
Change-Id: Id41717e265362303a17745303a907c9c8f4f4e12
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82057
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Chip Direct Mapping is exclusive to Windows; it allows specifying the
position where a chip is mounted. There are 8 positions and a _CDM
method should return 0xabcd0X, where X is the position.
Tested by booting Windows 11 on the StarLite Mk V, rotating the device
and checking the orientation is correct, where previously, it was
inverted.
Change-Id: If70c25288d835df7064b4051c43abeb2d6531f3b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81409
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As described in CB:83495, in AMD platforms, the bit 4 of CMOS Register A
is bank selection. Since the MC146818 driver accesses VBNV via Bank 0,
the value set in cmos_init() must not contain that bit.
To prevent RTC_FREQ_SELECT_DEFAULT from being incorrectly modified, add
an static assertion about the bank selection for AMD. Note that the
kernel driver also ensures RTC_AMD_BANK_SELECT isn't set for AMD [1].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/rtc/rtc-mc146818-lib.c?id=3ae8fd4157
BUG=b:346716300
TEST=none
BRANCH=skyrim
Change-Id: I6122201914c40604f86dcca6025b55c595ef609e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch adds new ISH PCI device IDs for Intel PTL-U and PTL-H.
Additionally, updates the ISH driver's `pci_device_ids` list to
include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: I280cfdb50e8d453e957cb4bccff3a7ee2fb3bd10
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83505
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
The 'Radio Frequency Interference Mitigation' DSM function 11
provides the desired status of the RFI mitigation.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 8.3 specification.
BUG=b:352768410
TEST=ACPI DSM Function 11 reflects the value of the SAR binary
Change-Id: I02808b0ce6a0a380845612e774e326c698ad1adc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The 'Energy Detection Threshold' DSM function 10 provides the desired
status of the EDT optimizations.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 8.3 specification.
BUG=b:352788465
TEST=ACPI DSM Function 10 reflects the value of the SAR binary
Change-Id: I2e2e9d4f5420020bd7540cb36fa8aebfedf62285
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
A previous commit splits out Cirrus display support from Bochs display
support, with both using the pre-existing Bochs config options for the
requested display resolution. Rename these config names to clarify they
are not only specific to the Bochs display driver.
Change-Id: Ie0a5e75731231bb768d7728867196c9ab5c53a00
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
