This patch adds google_chromeec_set_lightbar_rgb() to allow mainboards
to manually control the individual LED colors. This is useful for
providing visual feedback during early boot or platform-specific
events, such as low-battery warnings.
TEST=Build and boot google/fatcat.
Change-Id: I146006511ea727787ea496b0674b67fa950ce8f2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Occasionally when reading the EC version from ECRAM, the major
version fails to read and returns zero. To avoid having an incorrect
version reported, retry up to 10x with a 10ms delay between retries.
TEST=build/boot various Starlabs hardware, update the EC firmware,
verify the EC version is reported correctly every time.
Change-Id: I78d921e7230e8e180041097672661e744f70dde2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90834
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit e59c5abd13 ("ec/google/chromeec: Add
EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC") refactored cbi_get_uint32() to
write directly to the caller's buffer instead of using a local variable.
This caused uninitialized memory (containing garbage addresses) to be
passed to the EC as the return buffer during CBI reads.
In the case of google/zork, the call to
google_chromeec_cbi_get_board_version() returned garbage data (e.g.,
0xae6ccd05 vs 0x5) which caused incorrect code paths to be taken:
- variant_override_gpio_table() selected wrong GPIO tables based on
invalid board version comparisons
- variant_touchscreen_update() skipped touchscreen GPIO configuration
because variant_uses_v3_6_schematics() returned true for garbage
values
- variant_uses_codec_gpi() returned wrong value, preventing
headphone jack interrupt setup
These misconfigurations caused input devices (touchpad, touchscreen,
trackpoint) to be non-functional, despite being detected by the OS.
The fix restores the original behavior by using a local variable
initialized to 0, ensuring a clean buffer is always passed to the EC.
TEST=build/boot google/zork, verify board version is read correctly,
all input devices functional under Linux/Windows.
Change-Id: Ia7be0bcc588075ab5c994edc3d68e979cc01ac79
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90761
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reorganize the Kconfig file to improve structure and ensure proper
dependencies, to prevent options from showing in menuconfig. Drop
text string from EC_STARLABS_MERLIN as it should only be selected
at the mainboard level. Ensure all config options are only available
when one of the 3 Starlabs EC types is selected by the mainboard.
TEST=use menuconfig to build for Lenovo T440p, verify Merlin EC option
not shown.
Change-Id: I3f961342de25a22a8ebe1ae03dcf09c6ac2a0fb8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90627
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
On certain platforms, such as Qualcomm X1P42100 (Hamoa), the AP cannot
successfully execute the standard CHARGE_STATE_CMD_GET_STATE host
command while in the S0 power state. This is typically due to hardware
arbitration or access restrictions to the battery fuel gauge bus during
active operating states.
This patch introduces a mechanism to fallback to manual State of Charge
(SoC) calculation using dynamic battery metrics:
1. Add EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC Kconfig: Allows platforms
to opt-in to manual SoC calculation.
2. Refactor existing logic: The standard command is moved to an internal
static helper google_chromeec_read_batt_state_of_charge_cmd().
3. Unified API: google_chromeec_read_batt_state_of_charge() now switches
between the standard command and the raw/dynamic calculation at
compile-time based on the Kconfig selection.
By using ec_cmd_battery_get_dynamic(), the AP retrieves cached telemetry
from the EC. This avoids triggering synchronous bus transactions to the
battery, ensuring SoC data is available even when direct fuel gauge
access is restricted.
BUG=none
BRANCH=none
TEST=Build for Hamoa and verify SoC is correctly calculated via the
dynamic info path. Verify standard platforms still use the charge
state command path.
Change-Id: I4928017362140884762140884762140884762140
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Implement google_chromeec_read_batt_state_of_charge_raw() to
calculate the battery percentage using raw capacity metrics.
Unlike the standard charge state command, this function retrieves data
via EC_CMD_BATTERY_GET_DYNAMIC. It manually calculates the State of
Charge (SoC) by comparing remaining_capacity against full_capacity.
This provides a fallback mechanism for platforms where the high-level
CHARGE_STATE_CMD_GET_STATE command is not implemented or when working
directly with the fuel gauge's dynamic data cache.
Includes:
- Zero-capacity check to prevent division by zero.
- 100% clamping to handle fuel gauge rounding/calibration drift.
Change-Id: I86d6313884762140884762140884762140884762
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90615
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement google_chromeec_read_batt_state_of_charge() to retrieve the
current battery percentage from the Embedded Controller.
The function uses the CHARGE_STATE_CMD_GET_STATE host command to fetch
the State of Charge (SoC) as calculated by the EC's fuel gauge logic.
This provides a high-level percentage (0-100) suitable for power
management decisions or UI display.
Change-Id: Iec88476214088476214088476214088476214088
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add support for controlling charge LED brightness similar to the
existing power LED brightness control. This includes:
- New Kconfig option EC_STARLABS_CHARGE_LED
- Charge LED CFR option in cfr.h
- Implementation in ite.c using shared led_brightness array
- ECRAM_CHARGE_LED register definition
Refactor LED brightness enum values into shared led_brightness array
for reuse between power and charge LED controls.
EC changes for charge LED brightness
TEST=build/boot starlabs/lite_adl and verify LED control via CFR
Change-Id: I0f243d666e1fdc7d6df9859bb1cdcf460b6029ec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Ali Hamid <ali@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
GCC generates correct code for __builtin_bswapXX() on all architectures,
including ArmV4. It seems that whatever bug caused this to not work back
in commit 879ea7fce8 ("endian: Replace explicit byte swapping with
compiler builtin") has been fixed now. We can eliminate the swabXX()
functions and simplify the code.
All instances that had been calling these functions directly should have
been using real endianness conversions anyway.
Change-Id: I19713fd009aa5c0e01c4a42e0cf012364d6bed60
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90438
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The google_chromeec_is_charger_present function previously relied on
executing the EC_CMD_BATTERY_DYNAMIC_INFO command to check the
EC_BATT_FLAG_AC_PRESENT flag.
This commit refactors the function to directly read the host event
register (EC events B) and check for the EC_HOST_EVENT_AC_CONNECTED
event flag instead.
This approach is much more efficient as it avoids the overhead of
sending and receiving a full EC command (savings ~25-30ms), using a
readily available cached status instead.
TEST=Able to build and boot google/quenbi.
Change-Id: I2ec9aca5991394ed1d4998da37e074e9324bd672
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90334
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add ec_rgb_kb_color CFR option to select RGB keyboard color at
boot. Suppress regular keyboard backlight option when RGB keyboard
is present, as they are mutually exclusive.
TEST=build/boot google/mithrax, verify RGB keyboard option enabled,
all colors able to be set at boot.
Change-Id: I55848931248a70023c49b98190105679f2999ad9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add enum google_chromeec_rgbkbd_color with predefined color values
(OFF, RED, GREEN, BLUE, YELLOW, WHITE) and helper functions to
detect RGB keyboard support and set keyboard color. The color enum
is converted to RGB struct values internally for EC communication.
These will be used in a subsequent change adding support for setting
the RGB keyboard color at boot via CFR.
TEST=tested with rest of patch train.
Change-Id: I9afcbd8359e0fdc7c89e653165499f693367f5db
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Commit 04778ddd38 ("drivers/option/cfr: Remove old sm_object from
constructor") updated the function signature for CFR callbacks, but the
commits adding the fan and backlight controls were merged afterwards
without being adjusted accordingly. Do so here.
TEST=build/boot google/link with these CFR options enabled.
Change-Id: I9ea5224a820b014c4c8edb93e8a6b336ea6f58d0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Chromium OS EC has some specialized handling of chromebook specific
function keys on the keyboard top row, these have a function specific
action key code that is exposed to the OS and used to map their
position, and also a specific scancode that has to be mapped to a Linux
event code.
This adds the necessary mapping for KEY_HOMEPAGE, which is going to be
used in new devices.
The scancode picked is 0xe012, which maps to e02a or 0xaa, the
corresponding EC CL is:
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/7118961
BUG=b:446007724
TEST=flashed and tested on a brox board with chromiumos, checked the
code with evtest
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change-Id: I395721a342f507453dae19373df2f189ac1b5dac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90024
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Create a new header with CFR objects for keyboard backlight and
automatic fan control, which mainboards can include in their
setup menus in order to expose the options. The visibility of the
options are controlled by callbacks which test for device presence.
Change-Id: I2386b527f65b2e3b4ca43b9b65b69040abee00ad
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Allow enabling of automatic fan control via a setup option, while
preserving the functionality of the existing Kconfig symbol.
TEST=tested hooked up to a CFR option to toggle automatic fan control
at boot, with visibility controlled by fan presence, on a range of
ChromeOS devices with and without a PWM-controlled fan.
Change-Id: I0510c0d0bd79106036f77d59e04d455ee904ce6e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89830
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add google_chromeec_has_fan() to determine if a board has a fan or not.
The function first tries the EC feature flag (EC_FEATURE_PWM_FAN),
falling back to a RPM read test if the flag is unavailable.
TEST=tested hooked up to a CFR option to enable auto fan control at
boot, with option visibility controlled by fan presence, on a range
of Chromebooks with and without PWM-controlled fans.
Change-Id: I2a920709f0e6780c779a87568d6a8d18f817c76d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89829
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Currently, pressing the power button results in the EC powering off the
system without letting the OS cleanly execute its shutdown procedures.
Sending command 0x3e with an argument of 1 to the EC tells it to route
power button events to the host so that the OS can determine what to do.
This command was found in the ec/google/wilco code in coreboot, which is
used on Dell's Latitude Chromebooks. Based on the CONFIG_EC_GOOGLE_WILCO
help text, the "Wilco" ECs run a modified version of Dell's typical
Latitude EC firmware, so it is likely that the two implementations share
commands. Examining LPC traffic on the Latitude E6400 did show that
vendor firmware was sending a 0x3e command to the EC, and reimplementing
it in coreboot allowed power button events to be handled by the OS.
Change-Id: I5ded315270c0e1efbbc90cfa9d9d894b872e99a2
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The function incorrectly treated option values as array indices.
Update the function to search the LUT array for the value, and return
it if found, otherwise return the fallback value (not index).
Update call sites to pass EC value constants (SEC_30, FN_CTRL, etc.)
as the fallback values instead of numeric indices.
TEST=build/boot starlabs/starlite, verify charge limit and other EC
options work properly and values set properly in ECRAM using ectool.
Change-Id: Ie44d912932c8a3cec6ce0829c024788421cf89aa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add the battery design capacity and voltage offsets to the EC
definitons; these will be used by coreboot to calculate the
wattage which it'll use to set PL4.
Change-Id: Id0600ddd8ffaecab6004549ab51b7c06305d3c09
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89925
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This isn't a function change, it just reduces the number of
overrides.
Change-Id: I9178028b40c04fe52f4f549365828005cfe5f8be
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89911
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The featureset of Merlin is common, so adjust the Kconfig options
to avoid having the boards select all of them.
This is not a functional change.
Change-Id: Ie8d7afed750055274cdfde3f2f4f9b70fa47a8b1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
MAX_CHARGE and FAN aren't available for the Nuvoton EC, so
remove the dependency.
Change-Id: Ie087b1c4503a397621b8fd714564cc082150d7a6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89909
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the ability to set the keyboard backlight level at boot, controlled
by a setup option variable and restricted to devices which actually
have a backlit keyboard.
TEST=tested hooked up to a CFR option 'ec_kb_backlight' (added later in
the patch series) to set the keyboard backlight at boot, with
visibility controlled by backlight presence, on a range of Chromebooks
with and without keyboard backlight support.
Change-Id: I92eed62935d0333f548599860b7bbe22f6b9f2b4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89828
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Use defined constants from ec.h instead of hardcoded integer values
in all CFR enum definitions for improved readability and
maintainability.
Change-Id: I13b313d0c7a177fc689c3022256eb17125354599
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89881
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new function google_chromeec_has_kbbacklight() to check if the EC
has keyboard backlight capability. The function first tries the EC
feature flag (EC_FEATURE_PWM_KEYB), falling back to a read test if
unavailable. The EC command ec_cmd_pwm_get_keyboard_backlight() returns
-1 if the device does not have a keyboard backlight.
This function will be used in subsequent commits to guard setting the
keyboard backlight at boot and the visiblity of a CFR option setting.
TEST=tested hooked up to a CFR option to set the keyboard backlight
at boot, with visibility controlled by backlight presence, on a
range of Chromebooks with and without keyboard backlight support.
Change-Id: I74daf7a63f06239d2ba3915221555af494a9340f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89827
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`ToString(byte x)` is undefined behavior per the ACPI spec, which
causes Windows to discard the battery device status entirely.
Fix this and improve performance of the BRSX method by using an array
to store the characters read, calling ToString() only once at the end.
TEST=build/boot Win11 and Linux on google/rex, verify battery status
reported properly under both OSes.
Change-Id: I4e5aea3b2763a3c4433abe95c3a41d218fcd06c1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This is a more suitable place for these definitions as
it contains all other ECRAM offsets.
Change-Id: I12f52b7b27b24c49b6dfc3d4b8fa0718605d2d5f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89695
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `EC_STARLABS_ADD_ITE_BIN` Kconfig option is only meaningful on
Star Labs boards with an ITE EC, i.e. those with `EC_STARLABS_ITE`
selected. So, add a "depends on" line so that the former option is
only visible on applicable boards.
TEST=`EC_STARLABS_ADD_ITE_BIN` no longer shows up for qemu-q35.
Change-Id: Ifb40d8b432d2abeadba2a970010dac126e4b7418
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This is a legacy option that changed the charging frequency. It
is no longer needed as the "normal" frequency is faster and more
stable so remove it.
Change-Id: I73cf439d96d65f0be26595e42a4aedbc4388b850
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
None of these boards strictly "need" an ITE binary, so remove the
Kconfig option. This leaves the logic to add a binary untouched,
so it can be added if desired.
Change-Id: I6cd674a794cac51900b9a11c434b25e28a052b6a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89645
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are three options for the LID switch:
SWITCH_NORMAL 0x00
SWITCH_SLEEP_ONLY 0x01
SWITCH_DISABLED 0x02
Add these to coreboot to ensure they are set correctly.
Change-Id: I159111438eabd4abeb654be75fd80f29bd835055
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Enable _CRS method when EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE is
configured, even without EC sync IRQ support.
Previously, the _CRS method was only generated if EC_ENABLE_SYNC_IRQ or
EC_ENABLE_SYNC_IRQ_GPIO was defined, causing LPC generic memory range
configuration to be skipped on boards that don't use EC sync IRQ which
will results in no communication between kernel and EC.
This change ensures LPC memory range resources are properly exposed
in ACPI considering the hardware limitations where the EC sync IRQ GPIO
is not available for boards using LPC_GENERIC_MEMORY_RANGE.
BUG=437459757
TEST=Build and verify EC LPC memory range is configured in ACPI tables
on boards with EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE enabled
by dumping ssdt tables and also verify 'ectool version' cmd.
ectool version
RO version: ojal-0.0.0-2db24f9+
RW version: ojal-0.0.0-2db24f9+
Change-Id: If63dd631029d2756451fad71a5556bc0b23f507d
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89420
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a Kconfig option EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC for
reading firmware configuration from Unified Firmware and Second-source
Config (UFSC) [1] from EC CBI. As the UFSC already includes both the
32-bit FW_CONFIG and 32-bit SSFC, this option is incompatible with
EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG.
Also check the size of the data read from CBI.
[1] https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/6974727
BUG=b:448300592
TEST=emerge=skywalker coreboot
BRANCH=none
Change-Id: I2f686838d2f7a6f3eec3bd5224f89389340f7471
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89404
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Adds the `google_chromeec_ap_poweroff()` helper function to the ChromeEC
driver.
This new API wraps the `EC_CMD_AP_SHUTDOWN` command and sends it to the
Embedded Controller (EC). This provides a cleaner, standardized way for
other coreboot components to initiate an Application Processor (AP)
power-off sequence via the EC.
After sending the shutdown command, the function calls `halt()` as the
AP is expected to power down immediately after the EC processes the
command.
BUG=b:439819922
TEST=Verify shutdown on Google/Quenbi.
Change-Id: Iace6a66972791bb7acdb978dfeea67b6ff0fec68
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89223
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Generated using update_ec_headers.sh [EC-DIR].
The original include/ec_commands.h version in the EC repo is:
60aa7ccea9c include/ec_commands.h: Avoid lint errors
The original include/ec_cmd_api.h version in the EC repo is:
f47d8af4fbb include/ec_cmd_api.h: Define new API for EC_CMD_AP_SHUTDOWN command
Change-Id: I31d08bf4a0318ca3ba8c5bb5563acfe65830523b
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89296
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the ojal variant of the ocelot reference board by copying the
ocelot files to a new directory named for the variant.
BUG=b:437459757
TEST=1. Build emerge-ocelot
2. Run part_id_gen tool without any errors
Change-Id: Ic2fc86d89facae21b9bed898ebe518d316d953da
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Generated using update_ec_headers.sh [EC-DIR]
The original include/ec_commands.h version in the EC repo is:
9b00e297ee chipset: Add a host command to issue AP shutdown
The original include/ec_cmd_api.h version in the EC repo is:
0c77d31000 UCSI/PPM: Add ucsi_host_cmd tests
Change-Id: I9b27cdd946c2e20a996ef338ec57d08de4e26059
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
On warm reboot the PWR LED isn't automatically turned on by the EC.
Turn it on in the ramstage code, which allows to see when the reboot
has happened.
TEST=PWR LED is on after warm reboot on Lenovo X220.
Change-Id: Ia5fe3a52a6be622785c9588a94242ac0de0e19fa
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The EC doesn't care about POST codes send to port 80h and there's
no POST code display on the laptops, thus disable POST codes at all.
TEST=Lenovo X220 still boots.
Change-Id: Idf666796d3cbb504c6e68d84521359d7e2fe98d0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88999
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Users have requested to be able to disable the power LED, so add
this as an option.
Change-Id: I74da148c7891ab3dd5e5b692239670c9937ab302
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88890
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the custom function to set the value of a single GPIO and
use the generic function prototype defined in include/gpio.h instead.
Migrate all users of the old function to the new function.
Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.
Change-Id: I714eaf2115a455d327e6b2313dafd0e293bee8a7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When moving headers compilation can fail as pmh7.h is missing
the include for type bool. Add the missing include to make sure
future code refactoring works.
Fixed the error:
src/ec/lenovo/pmh7/pmh7.h:27:1: error: unknown type name 'bool'
Change-Id: Ib0a2489a0c461bf021168e98737ecb6062caa696
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add support for the MEC1653 EC as used by the Thinkpad T480/480s.
Change-Id: If82a7d27eb3163f51565c0c6e60cab60753611a7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-by: Máté Kukri <km@mkukri.xyz>
As far back as the x201, Lenovo's EC ACPI has treated 128 as an invalid
value, and returned a corrected value when it is reported/read from EC
RAM. Drop the ME workaround, which most H8-equipped boards select, in
favor of Lenovo's logic, since both accomplish the same result.
Change-Id: Icdc91e439ec30c8263de5810a13e75f7595472a5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88416
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
