set_cpu_type(): It determines the CPU type (big or small) that
is executing the function, and marks the global_cpu_type's array slot
which is corresponds to the executing CPU's index if the CPU type is
big core.
get_cpu_index(): It determines the index from LAPIC Ids. This is
required to expose CPPC3 package in ascending order of CPUs' LAPIC ids.
So, the function returns CPU's position from the ascending order list
of LAPIC ids.
TEST=Tested CPU index calculation, core type determination on Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If4ceb24d9bb1e808750bf618c29b2b9ea6d4191b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch implements a SoC overrides to check CPU privilege level
as the MSR is not consistent across platforms.
For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR
0x151.
BUG=b:211573253, b:211950520
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I515f0a3548bc5d6250e30f963d46f28f3c1b90b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch creates a `relative increment by 1` macro to let SoC
gpio pad configuration to be more flexible while adding support
for newer PCH SoC.
With this changes adding GPIO controller support for PCH-N would
become really simple without too much of code duplication.
For example: ADL-N has added `GPP_I` pins into community 1 hence,
the additional code for `PCH-N` whould appear incremetal to ADL-P.
> #define GPP_B 0x0
> #define GPP_T INC(GPP_B)
> #define GPP_A INC(GPP_T)
> #define GPP_R INC(GPP_A)
> #define GPD INC(GPP_R)
> #define GPP_S INC(GPD)
> if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
> #define GPP_I INC(GPP_S)
> #define GPP_H INC(GPP_I)
> #else
> #define GPP_H INC(GPP_S)
> #endif
> #define GPP_D INC(GPP_H)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie3b2183381b877da0a6e5a27f5176f0e21e0c9fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Add eMMC device into chipset.cb and keep it `off` by default.
eMMC device is applicable only for Alder Lake N SOC.
Change-Id: I2bc38ee5814688409feb7e4531c1daa5b54953c0
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Host device id 0x4619 is missed in few coreboot tables so that
coreboot can't recognize and config it properly.
Document Number: 690222
BUG🅱️214665785, b:214680767
Change-Id: I95908bdc0a736bafedb328dda2a00b5473de3d88
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Cannon Lake
and ensures disable_heci1() is guarded against this config.
Also, makes dt CSE PCI device `on` by default.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Idd57d2713fe83de5fb93e399734414ca99977d0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch checks if CSE's spi protection mode is protected or
unprotected. Returns true if CSE's spi protection mode is protected,
otherwise false.
BUG=b:211954778
TEST=Able to build and boot brya with this change. Calling
`cse_is_hfs1_spi_protected()` in coreboot is able to provide
the SPI protection status.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I23f1a1c4b55d8da6e6fd0cf84bef86f49ce80cca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
3. Make dt CSE PCI device `on` by default.
4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1
function disable at pre-boot instead of the dt policy that uses
`HeciEnabled = 0`.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The existing Sideband access is with the PCH P2SB. There will be future
platforms which access the TCSS registers through SBI other than the PCH
P2SB. This change abstracts the SBI with common API.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia6201762fe92801ce6b4ed97d0eac23ac71ccd37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change adds the Primary to Sideband Bridge(B0, D31, F1)
definition for the platform in order to maintain the common block
API build.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I1c4ddfce6cc6e41b2c63f99990d105b4bbb6f175
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4a81fd58df468e2711108a3243bf116e02986316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI
bit set for any slots of already existing boards, add set the option
PcieRpSlotImplemented=1 where appropriate.
Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Make use of the helper introduced in the parent change to deduplicate
the PCIe root port table.
Change-Id: I2dae4e4caf0a7ba3662889f3b31da0c3c299bc92
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add TGL-H support for the recently introduced code for differentiating
CPU and PCH root ports by adding the missing TGL-H port map.
Change-Id: Id2911cddeb97d6c164662e2bef4fdeece10332a8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The headers added are generated as per FSP v2511_04
Previous FSP version was v2471_02
Changes include:
- UPDs description update in FspsUpd.h and FspmUpd.h
- Adjust UPD Offset in FspmUpd.h
- Name change of UPDs in FspmUpd.h and FspsUpd.h
- Copyright year is updated in FspmUpd.h and FspsUpd.h
- Updated spd_upds and dq_upds structure variables in meminit.c
- Updated structure member of s_cfg->LpmStateEnableMask to PmcLpmS0ixSubStateEnableMask
in fsp_params.c
BUG=b:213959910
BRANCH=None
TEST=Build and boot brya
Cq-Depend: chrome-internal:4448696, chrome-internal:4445910
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com>
Change-Id: I39646c6812afbf622171361b8206daeacdaafac0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Currently coreboot and EC had different logic to interpret TCSS port
number which would break retimer update functionality since coreboot
would pass wrong port information to EC.
This change clones the implementation on Alder Lake which converts
the phyiscal port mapping to EC's abstract port mapping.
BUG=b:207057940
BRANCH=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: If4451598dbb83528ae6d88dbc1b65c206f24fe1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
TGL-LP only has 12 root ports, not 20. Correct the port map.
Change-Id: I3f5c69a2e7e3a2b8292c81beeac4ea6c7279d4b4
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Apollo Lake
and ensures disable_heci1() is guarded against this config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7ac0cad97fcd42b2c6386693319d863352356864
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Move the `configure_pmc_descriptor()` function to SoC scope instead of
having two identical copies in mainboard scope. Add a Kconfig option to
allow mainboards to decide whether to implement this workaround.
Change-Id: Ib99073d8da91a93fae9c0cebdfd73e39456cdaa8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch migrates common code API into SoC specific implementation
to drop CPU privilege level as the MSR is not consistent across
platforms.
For example: On APL/GLK, it's MSR 0x120 and CNL onwards it's MSR 0x151.
Also, include `soc/msr.h` in cpu.h to fix the compilation issue.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0b6f39509cc5457089cc15f28956833c36b567ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60898
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a config to let mainboard users choose the correct
state of HECI1(CSE) device prior to handing off to payload.
`DISABLE_HECI1_AT_PRE_BOOT` config to make HECI1 function disable
at pre-boot.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7e127816c506df3ac0cf973b69021d02d05bef4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We support all the ADL-P 15W/28W/45W SKU's and map them with the
latest VR configurations. These config values are generated by iPDG
application with ADL-P platform package tool.
RDC Kit ID for the iPDG tools
* Intel(R) Platform Design Studio Installer: 610905
* Intel(R) Platform Design Studio - Libraries: 613643
* Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345
* Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261
BUG=b:211365920
TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: Ida7a6df0422a9a3972646cb3bdd0112b5efa2755
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Enable CPPC entries generation, needed for Intel SpeedShift.
This can be tested by checking sysfs in Linux:
$ grep . /sys/devices/system/cpu/cpu?/acpi_cppc/*perf
The output should look like this, while the values may differ:
/sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf:28
/sys/devices/system/cpu/cpu0/acpi_cppc/lowest_nonlinear_perf:5
/sys/devices/system/cpu/cpu0/acpi_cppc/lowest_perf:1
/sys/devices/system/cpu/cpu0/acpi_cppc/nominal_perf:24
/sys/devices/system/cpu/cpu1/acpi_cppc/highest_perf:28
/sys/devices/system/cpu/cpu1/acpi_cppc/lowest_nonlinear_perf:5
...
Change-Id: I910b4e17d4044f1bf1ecfa0643ac62fc7a8cb51b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
FSP reserved memory is allocated inside cbmem which already gets
marked as a reserved memory region, so there is no need to do this
explicitly.
Change-Id: I39ec70bd9404d7bc2a4228c4364e4cc86f95d7c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
The PMC IPC method that is used for RTD3 support expects to be provided
the virtual wire index instead of the LCAP PN for CPU PCIe RPs.
Therefore, use the prior patches to update pcie_rp for CPU RPs.
Note that an unused argument to pcie_rtd3_acpi_method_status() was also
dropped.
BUG=b:197983574
TEST=add rtd3 node under pcie4_0 in overridetree for brya0, boot and
inspect the SSDT to see the PMC IPC parameters are as expected for the
CPU RP, and the ModPhy power gating code is not found in the AML for the
PEG port.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I84a1affb32cb53e686dbe825d3c3a424715df873
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60183
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Alder Lake chip.h file has pcie_rp_config entries for the CPU PCIe
ports, but the UPDs are not set. This patch hooks up those config
structs to the appropriate FSP-S UPDs.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ibb2375e66d53b4b7567dbe88b941cd720fdad927
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
When using a mixed memory topology with DDR4, it's not possible to boot
when no DIMMs are installed, even though memory-down is available. This
happens because the DIMM SPD length defaults to 256 when no DIMM SPD is
available. Relax the length check when no DIMMs are present to overcome
this problem.
Tested on system76/lemp10. Unit boots with and without DIMM installed.
Change-Id: I1cabf64fade1c06a44b6c3892659d54febc7a79a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
In some cases, partner may assign same clkreq on more than one devices.
This could happen when one device is in baseboard dev tree and another
one is in override dev tree.
This change adds a clkreq overlap check and shows a warning message
TEST=On brya, assigned one clkreq to 2 devices and found the warning
message
Change-Id: I2f701a19118f4702c227b17e43b6551591d9b344
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add minimal Device entries with just an _ADR for each of the PEG ports
for P and M chipsets (N does not have any PEG ports).
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Id1009004969729eddf7005fa190f5e1ca2d7b468
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The PMC IPC method used to enable/disable PCIe srcclks uses the
LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC
command expects the RP number to be its "virtual wire index"
instead. This new function returns this virtual wire index
for each of the CPU PCIe RPs.
BUG=b:197983574
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I5e9710f0d210396f9306b948d9dce8b847300147
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The PMC IPC method used to enable/disable PCIe clk sources uses the
LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC
command expects the RP number to be its "virtual wire index"
instead. This new function returns this virtual wire index
for each of the CPU PCIe RPs.
BUG=b:197983574
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7aa14a634dcd90c4817009db970fb209ae02c63d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Don't perform GPP lock configuration if
SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS config is not selected.
This patch fixes a compilation issue when APL/GLK boards are
failing while gpio_lock_pads() function is getting called from
IA common gpio block.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I392dc2007dba8169e480f82b58b7f0a1578bb09f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch modifies struct pad_config.pad type from `int` to 'gpio_t'
as pad offset inside GPIO community is unsigned type and also to
maintain parity with `struct gpio_lock_config.pad` type.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I15da8a1aff2d81805ba6584f5cc7e569faf456e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This patch renames struct gpio_lock_config variable `gpio` to `pad`,
to represent the pad offset within the GPIO community.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6bed99c401435c96c9543f99406a934d7141c575
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This patch fixes the documentation discrepancy of GPIO reset type
between PCH EDS and GPIO BWG. As per GPIO BWG, there are four GPIO
reset types in Alder Lake as below:
- Power Good - (Value 00)
- Deep - (Value 01)
- Host Reset/PLTRST - (Value 10)
- RSMRST for GPD/Reserved for GPP - (Value 11)
Hence, created two different reset types for `GPP` and `GPD`.
Also, replaced PAD_CFG0_LOGICAL_RESET_x macros with PAD_RESET().
BUG=b:213293047
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4b8742c7a0cc1dc420e3e22e34a16355294ed61b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Building an image for the Purism Mini v2 with `x86_64-linux-gnu-gcc-11`
fails with the format warning below as the size of size_t differs
between 32-bit and 64-bit.
CC ramstage/soc/intel/common/block/acpi/pep.o
src/soc/intel/common/block/acpi/pep.c: In function 'read_pmc_lpm_requirements':
src/soc/intel/common/block/acpi/pep.c:57:50: error: format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
57 | printk(BIOS_ERR, "Failed to retrieve LPM substate registers"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
58 | "from LPM, substate %lu, reg %lu\n", i, j);
| ~
| |
| size_t {aka unsigned int}
src/soc/intel/common/block/acpi/pep.c:58:62: note: format string is defined here
58 | "from LPM, substate %lu, reg %lu\n", i, j);
| ~~^
| |
| long unsigned int
| %u
src/soc/intel/common/block/acpi/pep.c:57:50: error: format '%lu' expects argument of type 'long unsigned int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
57 | printk(BIOS_ERR, "Failed to retrieve LPM substate registers"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
58 | "from LPM, substate %lu, reg %lu\n", i, j);
| ~
| |
| size_t {aka unsigned int}
src/soc/intel/common/block/acpi/pep.c:58:71: note: format string is defined here
58 | "from LPM, substate %lu, reg %lu\n", i, j);
| ~~^
| |
| long unsigned int
| %u
The variables `i` and `j` are of type size_t, so use the corresponding
length modifier `z`.
Fixes: 2eb100dd ("soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM")
Change-Id: I27bce0a6c62b1c1ebbca732761de2f59b042a5d4
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Building an image for the Purism Mini v2 with `x86_64-linux-gnu-gcc-11`
fails with the format warning below as the size of size_t differs
between 32-bit and 64-bit.
CC ramstage/soc/intel/common/block/irq/irq.o
src/soc/intel/common/block/irq/irq.c: In function 'assign_fixed_pirqs':
src/soc/intel/common/block/irq/irq.c:186:90: error: format '%lu' expects argument of type 'long unsigned int', but argument 5 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
186 | printk(BIOS_ERR, "ERROR: Slot %u, pirq %u, no pin for function %lu\n",
| ~~^
| |
| long unsigned int
| %u
187 | constraints->slot, fixed_pirq, i);
| ~
| |
| size_t {aka unsigned int}
CC ramstage/soc/intel/common/block/gspi/gspi.o
CC ramstage/soc/intel/common/block/graphics/graphics.o
CC ramstage/soc/intel/common/block/gpio/gpio.o
CC ramstage/soc/intel/common/block/gpio/gpio_dev.o
The variable `i` is of type size_t, so use the corresponding length
modifier `z`.
Fixes: b59980b54e ("soc/intel/common: Add new IRQ module")
Change-Id: I09f4a8d22a2964471344f5dcf971dfa801555f4a
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Retype the `pcie_port_coalesce` devicetree options and related variables
to better reflect their bivalue (boolean) nature.
Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Typically, FSP-M aka MRC debug log level defaults to `3`
meaning prints all `Load, Error, Warnings & Info` messages.
Sometimes it's too much information to parse even when users
aren't required to have such detailed information hence,
implement `fsp_map_console_log_level()` that maps coreboot console
log level to FSP-M debug log level and suppress verbose MRC debug
messages unless caller selects `HAVE_DEBUG_RAM_SETUP` config and
then the user can enable `DEBUG_RAM_SETUP`.
TEST=FSP-M debug log suggested default `SerialDebugMrcLevel`
UPD value is `2`. While this patch selects `HAVE_DEBUG_RAM_SETUP`
and user to select `DEBUG_RAM_SETUP` config to override
`SerialDebugMrcLevel` UPD value to '5' aka verbose.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Since TGL `spi_protection_mode` bit replaces the previous
`manufacturing mode` without changing the offset and purpose
of this bit.
This patch renames to `manufacturing mode` aka `mfg_mode` to
maintain the parity with other PCHs as part of IA-common code.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6d00f72ce7b3951120778733066c351986ccf343
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
