John Zhao 0f76a18c3a soc/intel/denverton_ns: Add the Primary to Sideband Bridge definition ... This change adds the Primary to Sideband Bridge(B0, D31, F1) definition for the platform in order to maintain the common block API build. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I1c4ddfce6cc6e41b2c63f99990d105b4bbb6f175 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>		2022-01-16 13:20:06 +00:00
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alderlake	vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04	2022-01-13 18:04:13 +00:00
apollolake	soc/intel/apl: Use Kconfig to disable HECI1	2022-01-11 19:18:02 +00:00
baytrail	src: Use 'stdint.h' when appropriate	2022-01-01 14:58:44 +00:00
braswell	Rename ECAM-specific MMCONF Kconfigs	2021-11-10 17:24:16 +00:00
broadwell	sb/intel: Use bool for PCIe coalescing option	2022-01-04 11:48:19 +00:00
cannonlake	soc/intel: Remove unused <string.h>	2022-01-05 17:37:49 +00:00
common	soc/intel/tgl/pcie_rp: add TGL-H support	2022-01-14 00:29:13 +00:00
denverton_ns	soc/intel/denverton_ns: Add the Primary to Sideband Bridge definition	2022-01-16 13:20:06 +00:00
elkhartlake	src/soc/intel: Remove unused <console/console.h>	2022-01-10 23:25:01 +00:00
icelake	src/soc/intel: Remove unused <console/console.h>	2022-01-10 23:25:01 +00:00
jasperlake	soc/intel/jsl: Replace dt HeciEnabled by HECI1 disable config	2022-01-14 00:33:23 +00:00
quark	Rename ECAM-specific MMCONF Kconfigs	2021-11-10 17:24:16 +00:00
skylake	src/soc/intel: Remove unused <console/console.h>	2022-01-10 23:25:01 +00:00
tigerlake	soc/intel/tgl: Replace dt HeciEnabled by HECI1 disable config	2022-01-14 00:33:14 +00:00
xeon_sp	src/soc: Remove unused <stdlib.h>	2022-01-10 23:30:56 +00:00
Kconfig
Makefile.inc	soc/intel/common/cse: Add support for stitching CSE components	2021-10-19 16:09:08 +00:00