Select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES and remove the
TODO from SOC_AMD_COMMON_BLOCK_HAS_ESPI.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I90e3bf3f196e22b428b01ea0437c1224702d2b44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Compile-time support of DPTC is controlled by
EC_ENABLE_AMD_DPTC_SUPPORT in each variant's ec.h file. This CL removes
EC_ENABLE_AMD_DPTC_SUPPORT and replaces it with the Kconfig value
SOC_AMD_COMMON_BLOCK_ACPI_DPTC.
Each variant's run-time support of DPTC continues to be controlled by
the variant's overridetree.cb "dptc_enable" value.
BRANCH=none
BUG=b:217911928
TEST=Build zork
TEST=Boot skyrim
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ic101e74bab88e20be0cb5aaf66e4349baa1432e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The CPPC table value for UEFI BIOS has been changed. The code has been
merged to AGESA. We can get the value by dumping ACPI table. Then we
align the coreboot code with the new value.
BUG=b:190420984
Change-Id: I091ab3bbc5f94961f8b366a3fa00f50f5c9fa182
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The size of the input parameter to RESET_SYSTEM svc call is expected to
be 4 bytes. Fix the reset_system type from enum to uint32_t.
BUG=b:243476183
TEST=Build and boot to OS in Skyrim with PSP verstage. Trigger a system
reset to ensure that the system is reset successfully.
Change-Id: I6319a1dfc89602722c1c2b1c4ee744493ae8b33f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67117
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only 16 MByte of the SPI flash can be mapped right below the 4 GB
boundary.
In case of a larger SPI flash size, still only the 16 MByte region
starting at 0xff000000 can be configured as WRPROT and be reserved for
the MMIO mapped SPI flash region. The next 16 MByte MMIO region starting
at address 0xfe000000 contain for example the LAPIC MMIO region, the
ACPIMMIO region and the UART/I2C controller MMIO regions which shouldn't
be configured as WRPROT. Reserving this region for the MMIO mapped SPI
flash would also result in an overlap with the MMIO resources mentioned
above.
In the case of a smaller SPI flash, reserving the full 16 MByte flash
MMIO region makes sure that the resource allocator won't try to put
anything else in the lower parts of the 16 MByte SPI mapping region.
To avoid the issues described above, always reserve/cache the maximum
amount of 16 MBytes of flash that can be mapped below 4 GB.
TEST=On boards with 16 MByte SPI flash chips, the resulting image of a
timeless build doesn't change with this patch. Verified this on Chausie
(Mendocino), Majolica (Cezanne), Cereme (Picasso) and Google/Careena
(Stoneyridge). On Mandolin (Picasso) with an 8 MByte flash, the
resulting image of a timeless build is different, but neither the
coreboot console output nor the Linux dmesg output shows any errors that
might be related to this change.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie12bd48e48e267a84dc494f67e8e0c7a4a01a320
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66700
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Voltage set based on standard configuration for each type.
TEST=build/boot google/skyrim, verify output in cbmem console log,
DMI type 17 table.
Change-Id: I9b1e68a9417e43cbb9c55b4c471664f3f9090342
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66981
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Since the frequency field is deprecated, print the max/configured MT/s
speeds instead.
TEST=build/boot google/skyrim, verify output in cbmem console log
Change-Id: Icee5af762ca37c3b2ec8c9a52a7f32fb848390b0
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66980
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Hook up newly-added method to convert from frequency to MT/s so that
boards which use (LP)DDR5 report their capability properly.
BUG=b:239000826
TEST=build/boot google/skyrim, verify SMBIOS Type 17 table reports
DRAM speeds correctly.
Change-Id: I694b6c227a8d8fb40c897053808bc79df330ed0c
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66954
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
smn_read32 is used in this file, so include the header file with the
function prototype so that the file compiles successfully.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5bef96cd08f22b3475e8b5ba4e984a6e1ab4da36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Since the I2C controller is part of the FCH, move the early
initialization from bootblock.c to early_fch.c which also matches what
the newer AMD SoCs do.
TEST=Successfully boots on google/liara and all I2C/cr50/TPM functions
appear to work properly
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I22d3a8888eaa34ea612da719c408c0083769e806
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66866
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The functionality of sb_enable_lpc is implemented in the common LPC
support code as lpc_enable_controller. This gets called by the common
lpc_early_init which also calls lpc_disable_decodes and lpc_set_spibase.
The lpc_set_spibase call was already done in bootblock_fch_early_init,
so the main change in code behavior is that now lpc_disable_decodes gets
called during early FCH initialization. The lpc_enable_port80 and
sb_lpc_decode calls after the lpc_early_init code will reenable some of
the decodes.
TEST=Successfully boots on google/liara, cbmem and dmesg logs look clean
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia58a6f609fa149a6c09ed99f08bdc4f05eb56f96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66841
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PCI config space of the SMBus device has a secondary mapping as an
ACPIMMIO bank. Since the PCI device is on bus 0, it's already available
early in boot after the enable_pci_mmconf call, so there's no need to
use the ACPIMMIO mapping instead of the PCI config space mapping.
Verstage on PSP could theoretically access the PCI config space via the
0xcf8/0xcfc register pair, but since verstage on PSP doesn't have the
ACPIMMIO mapping anyway, we won't loose any functionality here.
Change-Id: I5c8ce8de0a6ab0ed41e7e8a5980d0f0510aaa993
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This is sort-of reverts commit cbf290c692 ("soc/amd/sabrina: drop
CPPC code"), since it turned out that the CPPC feature is supported
on Sabrina (now Mendocino) despite this being missing from the
documentation I looked at when writing the patch referenced above.
Since the CPPC ACPI code generation functionality has been moved to
common code, this isn't a direct revert.
BUG=b:237336330
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1c059653eeae207d723c77e8a78b19c86e362296
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Mendocino has more eSPI decode ranges than Picasso or Cezanne. To
support these additional ranges, introduce a new Kconfig option
SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES that can be selected by
the SoCs that support the additional eSPI IO/MMIO decode ranges.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib761cdf201c35805d68cf5e8e462607ffd9fa017
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Now that we have functionality to get the minimal and nominal
frequencies, the corresponding fields in the CPPC config can now be
populated. If the HOB isn't present and/or the frequency values
could not be obtained, CPPC_UNSUPPORTED is still used; otherwise the
HOB-provided frequency in MHz is used for those two fields.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Change-Id: Id3257690a3388d44ceceb7ac4f1db3d49e195caa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66551
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add common AMD FSP functionality to get the nominal and minimal CPU core
CPPC frequencies. Those functions will be used in the _CPC ACPI object
generation in a follow-up patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Change-Id: I68ebdf610795d2673e0118a732f54f5f719b73c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66550
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SMI sleep entry handler will access the SMN space via the index/data
register at PCI config space offsets 0xb8 and 0xbc of the device at bus
0, device 0, function 0. This register pair is also used by other
software components running on the x86 cores after boot, so it should be
saved and restored at the beginning/end of the SMI handler if it
accesses SMN. The sleep entry SMI handler is a special case, since the
OS is already done at the moment we enter the sleep SMI handler which is
the last code that gets run on the x86 cores before entering S3/4/5.
BUG=b:237004699
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0980562ef8a61489082a81c71d6d00d0786d68cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Checking if the return value of the fsp_find_extension_hob_by_guid call
is NULL should make the code a bit easier to read.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6bdb07eab6da80f46c57f5d7b3c894b41ac23b8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The PSP currently uses a hard coded GPIO for the TPM IRQ. Not all board
versions use the same GPIO. This method allows the mainboard to pass
in the correct GPIO.
BUG=b:241824257
TEST=Boot guybrush and verify PSP message prints
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie05d095d7f141d6a526d08fbf25eb2652e96aa49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Since bootblock_soc_early_init gets called before
bootblock_mainboard_early_init which does the early GPIO setup, external
I2C level shifters that are controlled by GPIOs might not be enabled yet.
Moving the reset_i2c_peripherals call to bootblock_soc_init makes sure
that the early GPIO setup is already done when reset_i2c_peripherals is
called.
Haven't probed any SCL signal on the non-SoC side of the I2C level
shifters yet, but the waveform on the SCL pin of I2C3 on the SoC of a
barla/careena Chromebook doesn't have the longer than expected SCL
pulses any more.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If02140aef56ed6db7ecee24811724b5b24e54a91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This reverts commit 8b1c6c6cb3. With
updated APCB, eSPI configuration carries over to bootblock. Hence eSPI
does not need to be re-initialized in bootblock.
BUG=b:241426419
TEST=Build and boot to OS in Skyrim with PSP verstage.
Cq-Depend: chrome-internal:4929421
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I426b07329d4a0154d915381c99dcc9746b7a3d7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since the path after the chip keyword needs to point to the directory
that contains the chipset's chip.h file, change this from
soc/amd/rembrandt to soc/amd/mendocino.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I63334fbd59e74df491035b5cf7e296818cc02665
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66688
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The Cezanne CPPC ACPI table generation code also applies to Sabrina, so
move it to the common AMD SoC code directory so that it can be used for
Sabrina too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5ce082a27429948f8af7f55944a1062ba03155da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66400
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This reverts commit Ic152c295954d33ef1acddb3b06f0c6bbfbfb38ae.
There was a bug that caused the SMU to hang when writing port80. it has
since been resolved, so revert this workaround.
BUG=b:227201571
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I5f10e282ab03756c7dbfb48182940f979eb122e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66470
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
We want to extend the vb2ex_hwcrypto APIs on the vboot side to allow
passing 0 for the data_size parameter to vb2ex_hwcrypto_digest_init()
(see CL:3825558). This is because not all use cases allow knowing the
amount of data to be hashed beforehand (most notable the metadata hash
for CBFS verification), and some HW crypto engines do not need this
information, so we don't want to preclude them from optimizing these use
cases just because others do.
The new API requirement is that data_size may be 0, which indicates that
the amount of data to be hashed is unknown. If a HW crypto engine cannot
support this case, it should return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED to
those calls (this patch adds the code to do that to existing HW crypto
implementations). If the passed-in data_size value is non-zero, the HW
crypto implementation can trust that it is accurate.
Also reduce a bit of the console spew for existing HW crypto
implementations, since vboot already logs the same information anyway.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ieb7597080254b31ef2bdbc0defc91b119c618380
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
'Mendocino' was an embargoed name and could previously not be used
in references to Skyrim. coreboot has references to sabrina both
in directory structure and in files. This will make life difficult
for people looking for Mendocino support in the long term. The code
name should be replaced with "mendocino".
BUG=b:239072117
TEST=Builds
Cq-Depend: chromium:3764023
Cq-Depend: chromium:3763392
Cq-Depend: chrome-internal:4876777
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
The default state for the IRQ lines when the eSPI controller comes out
of reset is high. This is because the IRQ lines are shared with the
other IRQ sources using AND gates. This means that in order to not cause
any spurious interrupts or miss any interrupts, the IO-APIC must use a
low polarity trigger.
On zork/guybrush/skyrim the eSPI IRQs are currently working as follows:
* On power on/resume the eSPI controller drives IRQ 1 high.
* eSPI controller gets configured to not invert IRQ 1.
* OS configures IO-APIC IRQ 1 as Edge/High.
* EC writes to HIKDO (Keyboard Data Out) which causes the EC to set IRQ1
high.
* eSPI controller receives IRQ 1 high, doesn't invert it, and leaves IRQ
1 as high. This results in missing the first interrupt.
* When the x86 reads from HIKDO, the EC deasserts IRQ1. This causes the
eSPI controller to set IRQ1 to low. We are now primed to catch the
next edge high interrupt. This is generally not a problem since the
linux driver will probe the 8042 with interrupts off.
On S3/S0i3 resume since the eSPI controller comes out of reset driving
the IRQ lines high, we trigger a spurious IRQ since the IO-APIC is
configured to trigger on edge high. This results in the 8042 controller
getting incorrectly marked as a wake trigger.
By configuring the IO-APIC to use low polarity interrupts, we no longer
lose the first interrupt. This also means we can use a level interrupt
to match what the EC actually asserts.
We use the `Interrupt` keyword instead of the `IRQ` keyword in the ACPI
because the linux kernel will ignore the level/polarity parameters
for the `IRQ` keyword and default to `edge/high. `Interrupt` doesn't
have this problem.
The PIC is not currently configured anywhere and it defaults to an
edge/high trigger. We could add some code to configure the PICs trigger
register, but I don't think we need the functionality right now.
For zork and guybrush, this change is a no-op. eSPI is configured in
verstage which is located in RO, and we have already locked RO for
these devices. We will need to figure out how to properly set the
`vw_irq_polarity` for these devices.
BUG=b:218874489, b:160595155, b:184752352, b:157984427, b:238818104
TEST=On zork, guybrush and skyrim
$ suspend_stress_test --post_resume_command 'cat /sys/devices/platform/i8042/serio0/wakeup/wakeup35/active_count'
Verify keyboard works as expected and no interrupt storms are observed.
On morphius I verified keyboard and mouse work on windows as well.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4608a7684e34ebb389e0e55ceba7e7441939afe7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Change the SPL file from the 'cezanne' placeholder to a mendocino
filename. Also, move the default location to blobs/mainboard since
it's not board-agnostic.
BUG=b:241543152
BUILD=Enable feature and build amd/chausie
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I47647c5d926484e25e3f893e72c671554e277a56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Change the name of the whitelist file from the 'cezanne' placeholder
to a mendocino path/to/file. Also, as whitelist files won't be pushed
into a public repo, modify the path to point to site-local.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I49bbf1335606567735e36ed9bda1314bfc6247d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Modify sabrina's fw.cfg to point to the proper directory and use the
standard names, as released by AMD.
The name 'sabrina' was an alias used for the Mendocino product. The
public-facing builds have been using Cezanne blobs, renamed as Sabrina
or SBR, but can now take advantage of the appropriate blobs.
BUG=b:239072117
TEST=Build amd/chausie
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Id646844e41980802be1e39dce96e5adaace4311d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Boot issue while using FW slot A has been root-caused to the usage of
same TLB to map HW Crypto engines and SPI flash. With upcoming PSP
release, this TLB usage conflict has been resolved. Hence enable CCP
DMA.
BUG=b:240175446
TEST=Build and boot to OS in Skyrim with PSP verstage using CCP DMA.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I2b12adb7e94e489bf07963a6f9a829cf4b36ad5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Currently bootblock does not initialize eSPI if it is already done in
PSP verstage. But some other component is clobbering the eSPI
configuration causing timeouts in EC communication after the boot flow
hits x86. To workaround this issue, re-initialize eSPI in bootblock.
BUG=b:217414563
TEST=Build and boot to OS in Skyrim with PSP verstage.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I41c0b2816a106a6a547f3cb372693e1bb7f23734
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This function is only called from the same compilation unit, so turn it
into a static function.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5c2deaa46f69c763df9612e39415b37c60d631be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Switching off the pads of the internal crystal oscillator that connect
to the crystal on the board in S0i3 saves a little power, so enable it.
No measurements to quantify the power savings have been made. PPR #57243
revision 1.59 was used as a reference.
BUG=b:237647468
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I52f14ae5c614ad8ff0479b619de7164afa1e7648
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66336
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Add static check to ensure the reserved APOB DRAM space is the same size
as the MRC_CACHE region specified in the fmap.
Update sabrina APOB DRAM size to match the fmap.
TEST: Timeless builds identical. Test build with a larger MRC_CACHE than
APOB DRAM failed the assert as expected.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia14f6ef94b9062df0612fe96098b1012085ccf9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65878
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 78261e308de5361b2ff045091e8fb18cad2a5035.
Reason for revert: Now that PSP supports a soft fuse flag to toggle the
verstage serial logs, prevent PSP verstage from writing to the UART.
BUG=None
TEST=Build and boot to OS in Skyrim with PSP verstage. Ensure that PSP
verstage logs are not seen twice in the console.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7ef2d585c320ea5903197939136dd2049a71af95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
HW Modexp engine is verified to be working fine. Any verification
failures during PSP verstage are because the firmware body is not read
correctly. This might be because of the incorrect SPI ROM mapping. Hence
enable the HW modexp engine for keyblock, preamble and firmware body
verification.
BUG=b:240175446
TEST=Build and boot to OS in Skyrim with PSP verstage using one of the
FW slots.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8f6742630a7049354a24053fce28c477e53259e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Enabling them causes firmware keyblock/preamble and/or body verification
failure. Hence disabling them to use software based verification.
Re-enable them once the issue is root-caused.
BUG=b:217414563
TEST=Build and boot to OS in Skyrim with PSP and x86 verstage.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7e259ae5d790977d08afcb0a77f8d4f38c85f39e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66134
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently only SHA_GENERIC is used and does not need to be passed.
BUG=b:217414563
TEST=Build and boot to OS in Skyrim with PSP and x86 verstage.
Change-Id: Id705b1361fffaf940c51515e7f77d7fb0677fc4a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The SPI_RESTRICTED_CMD register is not a PCI configuration register. It
is memory mapped from the SPI bar.
Verified against PPR 55570 rev 3.16, PPR 56569 rev 3.03, and PPR 57243
rev 1.50
TEST=Compile tested only
Change-Id: I7c88aaea9ddac200644bb368be3bd4e9be47fd7b
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63305
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PSP expects PSP L2 directory address relative to the start of the SPI
ROM. Also PSP does not expect BIOS L2 directory address since it is an
entry in PSP L2 directory. Update the configuration such that PSP
verstage passes the right address to PSP.
BUG=b:217414563
TEST=Build Skyrim BIOS image. Ensure that PSP verstage passes the
address as expected by PSP.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8dc3aa4cb401d16a68da446f83eb9e68ee290fea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
On SoCs where PSP use A/B recovery layout, PSP expects PSP L2 directory
address relative to the start of the SPI ROM. Unfortunately there is
nothing in the EFS2 header to help identify such SoCs. Hence add a
config item to statically identify such SoCs.
Also when PSP uses A/B recovery layout, BIOS L2 directory is an entry in
the PSP L2 directory. Hence the address of BIOS L2 directory is not part
of EFS2 header. Thankfully PSP is able to identify the BIOS L2 directory
itself and does not expect PSP verstage to pass the address. Modify PSP
verstage to handle these updates.
BUG=b:217414563
TEST=Build Skyrim BIOS image. Ensure that PSP verstage returned the PSP
L2 directory as expected.
Change-Id: I2f856a62055c80b8e2db91c983832611a5f0389c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
PSP supports mapping FCH UART and verstage logs are visible in console.
Hence pre-bootblock cbmem contents do not have to be dumped to console.
BUG=b:238937687
TEST=Build Skyrim BIOS image. Ensure that PSP verstage logs in CBMEM are
not dumped to console again during bootblock.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8336e372b894d8b2f9bbfb21ab15a78527dcc4c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Skyrim uses second SPI pads for ESPI. Switch to it initialize ESPI in
verstage.
BUG=b:217414563
TEST=Build Skyrim BIOS image. Ensure that ESPI init is successful in PSP
verstage.
Change-Id: I6e3462e95c50d256b6c159ae1d854dd69a538bb0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
This allows the mainboard code to change FSP-M parameters depending on
parameters that are only known at run time and not at build time.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3e0e196a5d861acd7635c59db44ecf1970b73ce2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
