Since commit 34a7e66faa ("util/cbfstool: Add a new mechanism to
provide a memory map") the ext-win-base and ext-win-size option has been
replaced with the "--mmap" option.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I33cfb59d9dbe88c4f618301ac1506e3281b1a483
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
has_power_resource is a boolean, so use true, false instead of 0, 1.
Change-Id: I25b86ef577e072cfe3ef5dc2447113f11c51f747
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This patch enhances the readability of the CSE sync event
ELOG_TYPE_FW_CSE_SYNC by updating the event naming from "early and late
bootstage" to "pre and post memory."
BUG=b:379585294
TEST=boot verified on google/rex0 and google/rex64
without change:
```
rex-rev3 ~ # elogtool list
rex64-rev3 ~ # /media/usb/elogtool list
3 | 2024-01-01 22:25:59-0800 | Firmware CSE sync | Late CSE Sync
```
with change:
```
rex64-rev3 ~ # elogtool list
3 | 2024-12-17 02:22:36-0800 | Firmware CSE sync | Post RAM CSE Sync
```
Change-Id: Ia5db3ffb43b2ceac821de72ef9e88ed62e617d41
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Depending on the environment, the /data-in directory might be owned by
root and recent git versions refuse to work in these. So explicitly
mark /data-in as a safe environment.
Change-Id: Ia534928f759e50c2dfb1df8af653dee74c734603
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
There is no reason to stick to the point releases. So use the 3.19 base
image referring to the latest minor release instead. Also, update
installed packages to latest versions from that release.
Change-Id: Ic947f99ae7231918ec2e6105f8f3050a17fd1176
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
It seems the .bashrc is not loaded as intended and thus the bash
mechanisms never worked. So drop the bash invocations and replace them
with the ash shell. Also, don't modify the PATH variable since this is
done by the activation script.
Change-Id: I544a15c86c212e91ece59b583fb61dad37fca337
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Volumes are mounted with the command line parameter. Using the VOLUME
directive creates a persistent storage in a standard path, which is not
intended. So drop that and create equal directories in order to keep the
container working.
Change-Id: I9b3551cca34d846aba5ca5c89162f82baa6de768
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85724
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This to upgrade iasl from 20230628 to 20241212.
Change-Id: I4ae7073e46084024360ac0dd44e0df666cb32269
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This allows building coreboot with AddressSanitizer on ChromeOS.
Otherwise these memory leaks are detected which cause the build to fail.
Change-Id: Ife6114db99278c9a3fb8271410486b057ef822f6
Signed-off-by: Matt Turner <mattst88@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add target for building libstdcxx for a cross compile target using the
GCC source downloaded for a cross compiler build and linking against a
specified libc implementation.
BUG=NONE
TEST=Build libstdc++ for cross compilers, link against generated library
./util/crossgcc/buildgcc -t -p arm-eabi -P libstdcxx -l c,c++ -j128 \
--libstdcxx_include /tmp/picolibc
Change-Id: Ie0c06ffaeab632c27a992dee8abcc403cceabeed
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This patch introduces logging for the ELOG_TYPE_FW_CSE_SYNC event. This
event logs data related to CSE synchronization, along with the relevant
boot stage information.
BUG=b:305898363
TEST=boot verified on google/rex0 and google/rex64
Change-Id: I4d6d3c4e07ab8677feb6a8acf8d4c6604ab704b8
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85218
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Print the current project version in the console and in the generated
file with the pad configuration. This makes support easier, since we
know which version of the utility was used and whether we need to
re-generate the configuration file if an error was made in the latest
changes in the code. The version string includes several parts:
{major}.{minor}-{last commit in the intelp2m directory}-{?dirty}
The major is incremented if a new platform is added, minor - if changes
in functionality are made. Add dirty if the changes were not taken into
account using git.
Use the following command to print the version:
make version
Change-Id: Id2fd0757c003004af976309a44dbbfff0eb517a7
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67321
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- The generated map of long and short macros should correspond to the
reference ones for all pads (INTEL-SUNRISE-PCH/PAD-MAP). The test
suite is based on the generated macros of a real platform.
- generated field macros should correspond to the RO_FIELDS mask
(INTEL-SUNRISE-PCH/MASK);
- macros generated from the zero values bits of the DW registers should
correspond to the reference ones (INTEL-SUNRISE-PCH/EMRTY).
Use the following command in the console to run all the tests in the
project:
make test
Change-Id: I15c7483f120a330849d4bad036427be205b0911c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
- The generated map of long and short macros should correspond to the
reference ones for all pads (INTEL-LEWISBURG-PCH/PAD-MAP). The test
suite is based on the generated macros of a real platform.
- generated field macros should correspond to the RO_FIELDS mask
(INTEL-LEWISBURG-PCH/MASK);
- macros generated from the zero values bits of the DW registers should
correspond to the reference ones (INTEL-LEWISBURG-PCH/EMRTY).
Change-Id: Iec18462be8428c3f37d546332211a730ee589a2d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67133
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
- The generated map of long and short macros should correspond to
the reference ones for all pads (INTEL-APOLLO-PCH/PAD-MAP). The
test suite is based on the generated macros of a real platform.
- generated field macros should correspond to the RO_FIELDS mask
(INTEL-APOLLO-PCH/MASK);
- macros generated from the zero values bits of the DW registers
should correspond to the reference ones (INTEL-APOLLO-PCH/EMRTY).
Change-Id: I1c47edb31d24930068486c74147c5fbc9b18b4b6
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67134
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When calculating the GPR0 protection range, currently the offsets of
"CSE data partition offset" and FPT are not checked. Invalid pointer
dereference may lead to segmentation fault.
Ensure the offset is within the image size before accessing the pointer.
Change-Id: Ic9557d8fc8ae9e4c12114ee170bfc90d5e149df9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85016
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
Checkpatch suggests to use 12 chars of the commit id. So adjust the
submodule update script in order to be consistent.
Change-Id: I0e356066b6598f586054f940684c26b6e5db2169
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Similar to commit 8651731537 ("sconfig: Move config_of_soc from
device.h to static.h"), move these macros to static.h to separate
dependencies on device.h and static.h. These macros resolve to device
alises that are declared in the generated static_devices.h header, so
move them to static.h which includes static_devices.h.
Since static.h remains included in device.h, any source that uses these
macros should still compile correctly. Subsequent commits will add
static.h to files that need them, after which static.h can be dropped
from device.h.
Change-Id: I1c76ad749769591da9c102b11eb618e93b68bd7c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84676
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Some ChromeOS recovery images, such as for GRUNT, support multiple
boards / multiple bios/ec images, but do not break them out in a
'models' subdirectory like modern recovery images do. Instead,
they use a manifest.json to map the board name to the correct
bios/ec images. Add support for parsing out the info from here.
TEST=run `util/chromeos/crosfirmware.sh kasumi` and verify
that the correct shellball firmware is extracted from the recovery
image.
Change-Id: I64153ba16cb8328d65a0f088d05f04a969f6810f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
LLD deals with loadable segments in a different manner than BFD. The
MemSiz of the .text loadable section is padded till the virtaddr of the
.car.data section. Since .text is not loaded in ENV_CAR this does not
matter.
Change-Id: I1a0541c8ea3dfbebfba83d505d84b6db12000723
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84043
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ditaa is a utility to convert ascii block diagrams into bitmap graphics.
The latest sphinx-contrib-ditaa extension has not been updated since
2022 [1] and does not declare whether it is safe for parallel reading,
causing sphinx to issue a warning as we use the `-j auto` flag to
parallelize the build. It doesn't seem like anyone ever used it in the
docs aside from a now abandoned patch [2], so just remove it.
[1] https://pypi.org/project/sphinxcontrib-ditaa/
[2] https://review.coreboot.org/c/coreboot/+/37643
Change-Id: I460ce24aab203cbb416888787fc6e2c613d306b3
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84887
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Util_readme adds comments to the top of the generated Doc/util.md file
to indicate that it is generated and should not be edited directly.
These comments are not intended to show up in the rendered HTML output.
Since Markdown does not have a native way of adding comments, the
`[comment text]: #` syntax is often used to mark the line as a comment.
This takes advantage of the fact that references (often used throughout
the docs to list long URLs at the end of the document and reference them
in inline links) aren't rendered. However, MyST parser detects these as
a duplicate reference and issues a warning, since both lines use "//" as
the comment text.
Address this by using HTML comments, since Markdown also allows raw HTML
to be used. This seems like a cleaner option compared to repurposing
references and appears to have better compatibility with various
Markdown readers, which may be useful if someone wants to read the
documentation outside of doc.coreboot.org.
While we are here, regenerate Documentation/util.md and util/README.md
Change-Id: Ibd4f61009c01c7b64594d88c5d86e472f0ccaa6c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Use tabs instead of spaces and use one line per argument for better
readability.
Change-Id: Ic1893c3cd75f825cfddf29b53d3c5ddf8efcccc2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84854
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`cbfstool add-stage' crashes with a segmentation fault when generating
the program binary out of a romstage ELF containing relocation within
the data segment.
This commit makes `parse_elf_to_xip_stage()' look for the segment to
which the current relocation applies and compute the appropriate
location within the program binary.
This issue can be reproduced by defining a global variable with a
pointer to constant data. This variable is defined within the .data
section and contains a pointer to a constant which resides in the
.text section. As a result, a relocation entry is generated in the ELF
file.
struct my_struct {
const char *name;
};
struct my_struct my_global = { .name = "EXAMPLE" };
void fun(void)
{
printk(BIOS_DEBUG, "my_global.name=%s\n", my_global.name);
}
TEST=global data structure with a pointer to a constant does not make
cbfstool crash
Change-Id: I480b4b047546c8aa4e12dfb688e0299f80283235
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Intel platform boot policy setting blob is linked into FIT table
as an FIT4 entry. It is required for server executing CBnT and/or
PFR without a PCH.
Please refer to chapter 4.6 of the document in below link:
https://www.intel.com/content/dam/www/public/us/en/documents/
guides/fit-bios-specification.pdf
Tool usage:
./util/cbfstool/ifittool -f <binary> -a -n <cbfs name> -t 4 \
-r COREBOOT -s <max table size>
Change-Id: I0f9fc61341430b1a35a44d50b108dcfaf31cd11c
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Li, Jincheng <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84305
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The document was moved. The current URL gives a 404.
Change-Id: If6ca74a8bf47382100da048667976958961b9320
Signed-off-by: Daniel Maslowski <info@orangecms.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
According to CB:68982, add SPDX license headers to rex template
Makefile. Without this patch, build bot may report build failed.
BUG=none
TEST=Run create_coreboot_variant.sh and check Makefile
Change-Id: I7d100a2303be063590f1389a7eed8f9a52071241
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
When validating the FMAP against the IFD, the BIOS region is a somewhat
specical case, since the FMAP BIOS region usually does not match the IFD
BIOS region. Instead the FMAP region usually resides somewhere inside
the IFD BIOS region and the where depends on CONFIG_CBFS_SIZE.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I920a0ee246cfd2b4ae0870256357d4f285e1730d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Because we import the doimage_mv/Makefile.mk directly into the main
coreboot makefile, this was setting a global CFLAGS variable. That's not
a huge issue since coreboot doesn't use the global CFLAGS variable, but
it should be updated anyway.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iebe281ca891745c1f993df274ef75b1440059c85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Add support for SPI/flash, LPC/eSPI, MCH and
add pci vendor/product description.
References:
* CPU: Linux kernel
* GPU: Linux kernel
* GPU: https://dgpu-docs.intel.com/devices/hardware-table.html
* Intel Atom x6000E Series, and Intel Pentium and Celeron N and J Series
Processors for IoT Applications, February 2023, 636722
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Change-Id: Ida852f3c991cdd036d9c282f9cabceb23c765e25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75214
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When parsing XIP stages only compare PT_LOAD phdrs. Currently coreboot
stages only use PT_LOAD phdrs.
Change-Id: I305b25032a3c4a9fdefc76cad77fafdb862a604c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This fixes building inline assembly that uses SIMD registers. This is
for instance the case in the vboot library.
Change-Id: I24fa9d9f81430ea3ecd40de4304a10c6e235fece
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The `handle_range` function in `kconfig_lint` was failing to correctly
handle large hexadecimal values (64-bit value) due to limitations with
Perl's handling of standard integers.
This commit modifies the function to use the `bigint` pragma, enabling
it to handle arbitrarily large integers. This prevents issues with
64-bit hexadecimal values and ensures accurate comparisons for range
validation.
Change-Id: I402bb9bec9ba5bfb79b4185f35228c41d4a7b674
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84575
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot doesn't have a leading zero in gpio < 10.
E.g. G00 -> G0
Change-Id: I4558cec444ae2a081fbc0f49464354df222be6c9
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84190
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
IT8613E EC space is divided into 3 banks selectable by EC index 0x06
bits 6:5. Bank0 mostly contains the ITE EC registers known by
coreboot's ITE EC driver. Bank1 contains SB_TSI and PECI temperature
reading registers. Bank2, however, contains additional registers used
to select the temperature source reported in TMPIN reading registers,
PECI bridge registers as well as FAN2-5 controls and extra vectors.
Dump the additional banks using extra-selectors.
Based on non-public IT8613E Preliminary Specification V0.3.
TEST=Perform the IT8613E dump on Hardkernel ODROID H4+.
Change-Id: Ic8fdc56d1b0fbe811e13bc6b800512af654c1cb6
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Many sources include device.h and thus static.h, but many only need the
function declarations and type definitions, not the compiled devicetree
from sconfig. This causes many unnecessary recompiles whenever the
devicetree is updated due to the dependency. Address this by moving the
config_of_soc macro directly into the generated static.h header, as it
seems to be the only line in device.h that actually requires static.h.
For now, static.h remains included in device.h so that the build is not
affected. Subsequent commits will include static.h directly into sources
that actually need it, after which it can be dropped from device.h.
Some statistics for C objects:
Dell Latitude E6400 (GM45/ICH9):
669 total objects
181 depend on static.h
2 require static.h
Dell Latitude E6430 (Ivy Bridge/Panther Point):
693 total objects
199 depend on static.h
3 require static.h
Lenovo ThinkCentre M700 / M900 Tiny (Kaby Lake):
794 total objects
298 depend on static.h
23 objects require static.h
MSI PRO Z690-A (WIFI) DDR4 (Alder Lake):
959 total objects
319 depend on static.h
25 require static.h
The number of objects was determined by grepping the build log for
calls to CC, the number of objects that depend on static.h was
determined by grepping for calls to CC after touching static.h, and the
number of objects that actually require the static.h related lines from
device.h was determined by grepping for objects that failed to build
after removing the static.h lines from device.h and running make with
the --keep-going flag.
Change-Id: I7c40135bf2815093b81e47201c38b7d0a6ac8fa8
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Previously, Add_gpl() was only used with C and ASL source code files,
and was hard coded to use the C /* */ style comment, preventing it from
being used with files with other comment styles. Convert this into a
generic function for adding arbitrary SPDX license identifiers for
arbitrary filetypes. This replaces the hard coded GPL-2.0-or-later
string used in gma-mainboard.ads with a call to the new function.
This is also used to add SPDX headers to Kconfig and Makefile sources;
as previous commits added them to all such files in the tree.
Tested against logs from a Latitude E6430 (Ivy Bridge) and Precision
M6800 (Haswell) to check that license headers that were already being
generated did not change.
Change-Id: I24a1ccd0afb7045e878bf6eaae7a23f828a9240d
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The fields spi_block_size and base_addr of regular PSP header, lookup
and reserved of combo header, are constants. So we
move the setting statements to the creation functions.
Only update the count, size and fletcher in later function
file_dir_header.
TEST=Binary identical test on all AMD SOC platforms
Change-Id: I55c400e45536a57841b01d7c90d3fef9afa53e78
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
TEST=Binary identical test on all AMD SOC platform with use_combo
Change-Id: I41c5c6fb5acf92604dd06becf1eda680a1fab545
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84131
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The new layout definition has a new way to support combo.
It packs multiple ISH entries into PSP L1 directory.
TEST=Identical test on all AMD platform
Change-Id: If573cdeaeb56e95d2fed235c9337fab82d622757
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This just orders the EXCLUDED_DIRS directories in a row based manner,
since there are quite a few them now and it is arguably easier to read
and to add new directories if they are written in a row based fashion.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I802aece355bba4900e71824d802c4b2438726e84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
ifdtool will exit with success while encountering an unrecognized flag.
For example, -g is a newly introduced flag, when we want to call it with
an older version of ifdtool, we will get the return value 0 and cause
confusion.
This patch change the exit status for unrecognized flags and doesn't
change the exit status for -h and -?.
BUG=b:362983041
BRANCH=none
TEST=futility update --servo --image /var/tmp/image.bin --quirks
unlock_csme on the servo host with old ifdtool
Signed-off-by: Hsuan Ting Chen <roccochen@google.com>
Change-Id: I046ad7ec790cda41a98a1de5cd730d32f65a9067
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Currently, cbfstool prints the following error message when the added
file doesn't fit in the region:
E: Could not add [file, 1024 bytes (1 KB)@0x0]; too big?
It requires manual inspection to know the space left in the region. To
make that easier, also print the maximum empty CBFS entry size in the
error message:
E: Could not add file [header 76 + content 1024 bytes (1 KB)] @0x0;
Largest empty slot: 512 bytes
Change-Id: I00bcc83abe8b0a33dcd7b75521e6cfccd8953661
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
