Improve host EC command debugging with timestamps and duration for
better analysis, this feature can be enabled by selecting the config
EC_GOOGLE_CHROMEEC_HOST_CMD_DEBUG.
BUG=none
TEST=Brox/lotso device successfully built and booted. Debug messages
confirmed in device logs only when the specific configuration is
selected. Sample print: "EC HOST CMD Duration: 661 us, Command: 0x4b,
version: 0x0"
Change-Id: I8ab89830ede940d2237ad21187b137dca9689fb0
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Move the Q-Events used by the merlin EC to their respective
files, i.e. `Q0B` for Battery Status Update to battery.asl.
This means that only revelant events will be included.
Change-Id: Ib41fbafd79b999409a520361a4d372902d878794
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85945
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove variant directories for boards that haven't or won't be
ported, or that now use the common "Merlin" code.
Change-Id: Ibfdd858c6460a1291d6a15bb7eccee9e9006adff
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit introduces an automatic linkage between the Microchip
EC (EC_GOOGLE_CHROMEEC_MEC) and ACPI memory
mapping (EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) options. This linkage is
enabled when the Microchip EC is selected.
Certain data registers in Microchip ECs cannot be accessed via I/O
space. Instead, an indirection mechanism is required for register
access. When using such an EC, coreboot must publish ACPI information
to access these data registers through ACPI data ports 66h/62h.
Analysis of the coreboot codebase has revealed that the
EC_GOOGLE_CHROMEEC_MEC and EC_GOOGLE_CHROMEEC_ACPI_MEMMAP options are
consistently used together. This commit streamlines this dependency by
linking the two options.
TEST=/sys/class/power_supply/BAT0/* reports consistent values on
fatcat board.
Change-Id: Ib4120a6d0ba2f4785e8b07b33943010e58bcbdd3
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85886
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is in preparation to store options in EFI variable store, rather
than CMOS. However, some still need to stay in CMOS, so that they can
be accessed via ACPI.
Change-Id: Idb094456543c75b59a8ddd80b58eb4fa1e10144f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76582
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is done by edk2, so there isn't any need for coreboot to do it.
Change-Id: I947d5d2f7512cc910963054dfbe6b5dc0f00462a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add an option to set the Power LED to a lower brightness level
Change-Id: I39507d4f2e572ca31ad982ce0d730a0d00f6ca32
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85702
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ensure any reads or writes to the EC memory, are performed with ECRD
(Read) and ECWR (Write) as these methods use a mutex.
Also, use local variables to cache reads of the same variable within
a given ACPI method.
This solves:
Initialized Arguments for Method [ECRD]: (1 arguments defined for method invocation)
Arg0: 00000000967261a4 [RefOf] <Node> Name ECPS RegionField 000000007d4b8073
ACPI Error: Aborting method \_SB.PCI0.LPCB.EC.ECRD due to previous error (AE_BAD_PARAMETER) (20230628/psparse-529)
ACPI Error: Aborting method \_SB.PCI0.LPCB.EC.ADP1._PSR due to previous error (AE_BAD_PARAMETER) (20230628/psparse-529)
Change-Id: I0bbb538017cc004bff1989a8017ccfcd1ba9ab5c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84734
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow boards that use the merlin EC to disable the lid switch.
Change-Id: Ib5f71ce46e9e97a1a02e4ea5af6aeb094ee6fad7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84634
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow boards that use the merlin EC to configure the charging speed,
as all versions of the merlin EC support this.
All coreboot does it write a value to the EC RAM and the EC will
handle the rest.
Change-Id: I46faa540530c5bd7f5473021561380213158152e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Commit 50b7976bb2 ("ec/starlabs/merlin: Remove ITE mirror
functionality") removed the mirror_flag param from the EC code, but
some remnants were left behind in the platform and mainboard code.
Drop these unused bits.
TEST=build/boot starlabs/starlite_adl
Change-Id: I6eb8c9a6ef8f92e2d92081b8451cef8d7246ff7e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This change adds support for the generic LPC memory range configuration
in the EC ACPI code.
If CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE is enabled, the
EC will use the generic LPC memory range for EMEM related communication
between EC and AP Firmware. This is useful for platforms that do not
have a dedicated IO range like accessed EMEM through port 62/66 or
through LPC at 900h.
The generic LPC memory range is defined by the _SB.PCI0.LPCB.GLGM()
method. This method returns the base address and size of the memory
range.
Update the comment section to reflect the alternative source for EMEM
data when CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE is enabled.
BUG=b:354066052
TEST=Build and boot on a device with
CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE enabled.
Change-Id: I8038e2827ec7e301bad3a5a58df007f3a448bad7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit introduces a new function,
google_chromeec_is_barrel_charger_present(), which checks if a barrel
charger is present.
The function uses the following logic to determine if a barrel charger
is present:
- If both a barrel charger and USB-C PD are present, then the barrel
charger takes precedence over USB-C PD. As a result,
google_chromeec_is_usb_pd_attached() will return false. This logic can
be used to deterministically say if a barrel charger is present even
when both a barrel charger and USB-C PD are attached.
- If an AC charger is detected and USB-C PD is not present, then a
barrel charger must be present.
This change allows the EC to accurately detect the presence of a barrel
charger, even when a USB-C PD charger is also attached.
BUG=b:377798581
TEST=Able to read the charger status correctly while booting
google/fatcat.
Experiment #1:
- USB-C PD Attached = yes
- Barrel Attached = No
- Charger Detected = Yes
```
fatcat-rev257 ~ # cbmem -c | grep -5 "ac_charger_present"
[INFO ] ac_charger_present: yes
[INFO ] usb_pd_present: yes
[INFO ] baseboard_devtree_update: Barrel Absent
```
Experiment #2:
- USB-C PD Attached = No
- Barrel Attached = Yes
- Charger Detected = Yes
```
[INFO ] ac_charger_present: yes
[INFO ] usb_pd_present: no
[INFO ] baseboard_devtree_update: Barrel Present
```
Experiment #3:
- USB-C PD Attached = Yes
- Barrel Attached = Yes
- Charger Detected = Yes
```
[INFO ] ac_charger_present: yes
[INFO ] usb_pd_present: no
[INFO ] baseboard_devtree_update: Barrel Present
```
Experiment #4:
- USB-C PD Attached = No
- Barrel Attached = No
- Charger Detected = No
```
[INFO ] ac_charger_present: no
[INFO ] usb_pd_present: no
[INFO ] baseboard_devtree_update: Barrel Absent
```
Change-Id: I9644f0dec057f95bb0a22cdc18edc1a0234ee3a9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This patch adds a new API `google_chromeec_is_below_critical_threshold()
` to check if the battery level is below the critical threshold.
The API uses the existing `ec_cmd_battery_get_dynamic()` command to
retrieve the battery flags and checks the `EC_BATT_FLAG_LEVEL_CRITICAL`
flag to determine if the battery level is critical.
This API can be used by other components to query the battery critical
status and take necessary actions, for example, while the system is
booting with low battery fuel with and/or without an AC
charger attached.
This addresses the need to implement a low battery charger icon and
detect when the system is booting with low battery fuel. The existing
`google_chromeec_is_battery_present_and_above_critical_threshold()`
API is not suitable for this purpose because any negative decision
(like battery not present and/or battery is critically low) implemented
around this existing API will also render the lower battery indicator
when the system is booting into battery cut-off mode. Ideally, we do not
wish to render any icon and simply allow boot to the OS during system
battery cut-off boot.
BUG=b:377798581
TEST=Able to read the battery status correctly while booting
google/fatcat.
Change-Id: Id1fc1df374fb4c663becc371c69b285d8b9957ff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85759
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This patch introduces a new API, `google_chromeec_is_charger_present()`,
to determine if a charger is connected.
The API leverages the existing `ec_cmd_battery_get_dynamic()` command
to retrieve battery flags and checks the `EC_BATT_FLAG_AC_PRESENT`
flag to ascertain charger presence.
Other components can leverage this API to query the charger status,
which is particularly useful for distinguishing between barrel chargers
and USB-C chargers after relying on the
`google_chromeec_is_usb_pd_attached()` API.
BUG=b:377798581
TEST=Able to read the charger status (w/ barrel and/or w/ USB-PD)
correctly while booting google/fatcat.
Change-Id: Iadf81400f71a51c093f71fe995cacc107c50c7af
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85758
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change introduces a new API, `google_chromeec_is_usb_pd_attached()`
which checks the current status of the USB-C port and returns whether a
USB Power Delivery (PD) charger is currently connected.
This API is useful for determining if the system is currently being
powered by a PD charger.
BUG=b:377798581
TEST=Able to read the PD status correctly while booting google/fatcat.
Change-Id: I47c934ee8a7563d4ba5124bff5613e61dd66e923
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add support for indexed IO for ec communication, Indexed I/O allows
memory access using a single I/O port base address usually called an
index register and another port address called a data register.
BUG=b:379224648
TEST= able to build nissa/trulo.
Change-Id: I6c1aab3fc914eb5af2736a8ea3adf447040905e0
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch adds support for the Intel Virtual Button driver, which
reports whether a tablet is docked or undocked. The GPIO used for
detection is hardcoded to GPP_F15 for now, specific to the
`mb/starlite_adl` board.
The GPIO value is returned to the HID driver via the `_STA` and
`VGBS` methods. These methods ensure proper notification to the OS,
allowing it to show or hide the virtual keyboard depending on the
docking status.
Tested on `starlite_adl` with Ubuntu 24.04, confirming the virtual
keyboard appears when the tablet is undocked and hides when docked.
This was verified with ACPI debug enabled, as dmesg does not
report the state of the GPIO.
Change-Id: I574a1b2d3907b2341a0dfdc412151d574ba4848e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83879
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change allows the Chrome EC (CREC) ACPI device to publish the LPC
Generic Memory Range (GMR) address range using the _CRS method.
The Google CREC driver can now parse this information to determine the
MMIO address map, enabling access to the LPC GMR register space.
This addresses the issue where the CREC driver was unable to
automatically determine the LPC GMR base address.
TEST=Able to build and boot google/brox.
without this patch:
brox-rev0 ~ # cat /proc/iomem | grep fe0
fe000000-fe00ffff : INTC1026:00
fe000000-fe00ffff : intel_scu_ipc
fe03e000-fe03efff : 0000:00:1e.0
fe03e000-fe03e1ff : lpss_dev
fe03e000-fe03e1ff : serial
fe03e200-fe03e2ff : lpss_priv
fe03e800-fe03efff : idma64.4
fe03e800-fe03efff : idma64.4 idma64.4
with this patch:
brox-rev0 ~ # cat /proc/iomem | grep fe0
fe000000-fe00ffff : INTC1026:00
fe000000-fe00ffff : intel_scu_ipc
fe03e000-fe03efff : 0000:00:1e.0
fe03e000-fe03e1ff : lpss_dev
fe03e000-fe03e1ff : serial
fe03e200-fe03e2ff : lpss_priv
fe03e800-fe03efff : idma64.4
fe03e800-fe03efff : idma64.4 idma64.4
fe0b0000-fe0bffff : GOOG0004:00
Change-Id: Ib3ea3e2a482f9eceaa8c15e38b7e708b156bc978
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85603
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change simply replaces 0x80 with a top level constant called
ACPI_NOTIFY_CROS_EC_MKBP. There are no functional changes.
BUG=b:343288326
TEST=Build
Change-Id: Ia476263620acc269f9dd8a6b3c9e5e247b403aee
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Add API to get Power Delivery (PD) Chip info which includes vendor ID,
product ID and firmware version(if any).
BUG=None
TEST=Build Brox BIOS image and boot to OS.
Change-Id: I4cc4493ac64d44076877fee633488c95cd09807e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add support to define ACPI devices for USB-C ports using UCSI. When
defining the typec configuration do not set mux/retimer information.
cros_ec_ucsi does not support setting USB muxes.
BUG=b:349822718
TEST=emerge-brox coreboot chromeos-bootimage. Boot to OS on brox,
confirmed that there are ACPI devices for each USB-C port and
cros_ec_ucsi correctly matched the ACPI devices ("ls -l
/sys/class/typec" with an update to add an ACPI match table to
the cros_ec_ucsi driver).
Change-Id: Ie7c281fe2a7fab705d3c238dcc4be68c93afd652
Signed-off-by: Jameson Thies <jthies@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84404
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit refactors the long battery string implementation to include
caching of the EC response for battery information (model, serial, and
manufacturer).
This optimization reduces resume time by approximately 63ms by
minimizing communication overhead between the AP and EC.
BUG=b:366338622
TEST=Verified on google/tivviks_ufs:
* Long battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING is enabled.
* Short battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING=n.
Change-Id: I32ae5b5e618f20335f3d344811a97f1416df529e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Older ChromeOS devices (pre-CR50) do not support reading long battery
strings. This commit adds a Kconfig option,
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING, to enable or disable this
feature.
This allows devices with TPM_GOOGLE (CR50/TI50) to read and display
long battery strings, while older devices like google/link, wolf, samus,
and chell will continue to display only the first 8 characters.
This change ensures compatibility with older devices while enabling
the display of complete battery information on newer platforms.
BUG=b:366338622
TEST=Verified on google/tivviks_ufs:
* Long battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING is enabled.
* Short battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING=n.
Change-Id: I7859809278b7e926bbe8beb1a0a9e12c7e6c220d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84352
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reporting the battery serial number to ACPI causes Windows to say
there isn't a battery present. As the serial number is as useful as
waterproof towel, don't do it.
Change-Id: I97a28b1d8d7bb45ea4790c8125cd3c1bc52ee5f9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
As the merlin EC supports both the IT8987 and IT5570, move the
check into the code so the same variant directory can be used
for both chips.
Change-Id: I8c43a367e42f7e56ddd26b1c8fe7bf4b275d4ac3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83632
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of using defines for command IDs and argument values, use enums
to provide more type safety. This also has the effect of moving the
command IDs to a more central location instead of defines spread out
throughout the header.
Change-Id: I788531e8b70e79541213853f177326d217235ef2
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This board now uses merlin so it can be removed.
Change-Id: I6036695ccf80b0a7d6e6463d26e5b32aa6cb9d57
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Remove the ITE mirror functionality; all devices will mirror
automatically when they exit G3, and this is good enough.
Change-Id: I9b82e1b1386b4607dfe7da9b25ba432ec0303cf8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83629
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
System76 EC since system76/ec@80cfa91b9f ("acpi: Report RPM values
instead of raw tachometer values") performs the RPM calculation itself
and stores it in EC RAM where previously the raw tachometer values were
saved. The SBIOS is no longer required to make the conversion.
Change-Id: I82a4e25a8ce0f274b2d98e7ff2b12595acf6c3c5
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Since the EC and PD firmware sources are now limited to two options -
'none' and 'external' - drop the choice selection and make the
EC and PD external options independent.
TEST=build google/lulu with external EC binary using existing defconfig
Change-Id: Ie37ff3a188b414fd099fbb344858bca4df419086
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83639
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In preparation for dropping the Chrome-EC submodule, remove the ability
for Chrome-EC and PD components to be built as part of coreboot.
These components have not been used or buildable for many years.
Change-Id: Ibf6bd43e755cf5b4d2aa8a42f38dc52e7023e9b3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83638
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Multiply before dividing to improve accuracy of the result.
Change-Id: I974cad3af4e1f86ae58e90c68db463fc436223af
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83619
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ucsi_enabled flag is no longer used by the EC. Update coreboot to only use only EC_FEATURE_UCSI_PPM to determine whether UCSI is enabled.
BUG=b:319124515
TEST=emerge-brox coreboot chromeos-bootimage
Cq-Depend: chromium:5664227
Change-Id: Ia9d820c637e56a527fd90f45b1848158a960dee7
Signed-off-by: Abhishek Pandit-Subedi <abhishekpandit@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83252
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Forest Mittelberg <bmbm@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Chrome EC currently supports two ways to read battery strings on
ACPI platforms:
* Read up to 8 bytes from EC shared memory BMFG, BMOD, ...
* Send a EC_CMD_BATTERY_GET_STATIC host command and read strings from
the response. This is assumed to be exclusively controlled by the OS,
because host commands' use of buffers is prone to race conditions.
To support readout of longer strings via ACPI mechanisms, this change
adds support for EC_ACPI_MEM_STRINGS_FIFO (https://crrev.com/c/5581473)
and allows ACPI firmware to read strings of arbitrary length (currently
limited to 64 characters in the implementation) from the EC and to
determine whether this function is supported by the EC (falling back to
shared memory if not).
BUG=b:339171261
TEST=on yaviks, the EC console logs FIFO readout messages when used in
ACPI and correct strings are shown in the OS. If EC support is
removed, correct strings are still shown in the OS.
BRANCH=nissa
Change-Id: Ia29cacb7d86402490f9ac458f0be50e3f2192b04
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit simply adds support for a Do Not Disturb key. HUTRR94 added
support for a new usage titled "System Do Not Disturb" which toggles a
system-wide Do Not Disturb setting.
BUG=b:342467600
TEST=Build and flash a board that generates a scancode for a Do Not
Disturb key. Verify that KEY_DO_NOT_DISTURB is generated in the Linux
kernel with patches[0] that add this new event code using `evtest`.
[0] - https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git/commit/?id=22d6d060ac77955291deb43efc2f3f4f9632c6cb
Change-Id: I26e719bbde5106305282fe43dd15833a3e48e41e
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82997
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Forest Mittelberg <bmbm@google.com>
Add support for an Accessibility key. HUTRR116 added support for a new
usage titled "System Accessibility Binding" which toggles a
system-wide bound accessibility UI or command.
BUG=b:333095388
TEST=Build and flash a board that contains an accessibility key. Verify
that KEY_ACCESSIBILITY is generated in the Linux kernel with patches[0]
that add this new event code using `evtest`.
```
Testing ... (interrupt to exit)
Event: time 1718924048.882841, -------------- SYN_REPORT ------------
Event: time 1718924054.062428, type 4 (EV_MSC), code 4 (MSC_SCAN), value a9
Event: time 1718924054.062428, type 1 (EV_KEY), code 590 (?), value 1
Event: time 1718924054.062428, -------------- SYN_REPORT ------------
Event: time 1718924054.195904, type 4 (EV_MSC), code 4 (MSC_SCAN), value a9
Event: time 1718924054.195904, type 1 (EV_KEY), code 590 (?), value 0
Event: time 1718924054.195904, -------------- SYN_REPORT ------------
```
[0] - https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git/commit/?id=0c7dd00de018ff70b3452c424901816e26366a8a
Change-Id: Ifc639b37e89ec251f55859331ab5c2f4b2b45a7d
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82996
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Forest Mittelberg <bmbm@google.com>
Generated using update_ec_headers.sh [EC-DIR].
The original include/ec_commands.h version in the EC repo is:
d0771e49e7 MKBP: Increase key matrix size
The original include/ec_cmd_api.h version in the EC repo is:
d0771e49e7 MKBP: Increase key matrix size
Change-Id: I4f3dfc3f145e50e6114894352cdc118ad5a9565b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82995
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Forest Mittelberg <bmbm@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Under Windows ACPI, GpioInt and _PRW must be mututally exclusive within
the scope of a device, otherwise a BSOD occurs with an ACPI_BIOS_ERROR.
To enforce this, only use _PRW when EC_ENABLE_SYNC_IRQ_GPIO is not set.
If both EC_ENABLE_WAKE_PIN and EC_ENABLE_SYNC_IRQ_GPIO are set, then
ensure that the GpioInt is flagged as ExclusiveAndWake (vs just
Exclusive) so that the CREC device is still able to wake the device
as needed.
TEST=Build/boot google/{nocturne,frostflow} to Win11 w/ sync_irq_gpio
and wake_pin both enabled.
Change-Id: Ia59cce2ee12bfc8d3ac0173a7a4ec88d7079a958
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82233
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the EC doesn't know a value, it will report it as 0xffff. In these
cases, calculate a value to used based on others. For example, if the
EC doesn't know the last full charge capacity, report the design
capacity to the OS.
Change-Id: I310555ff913c2e492bbaec4d77281ac32c0de7a3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81408
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename the BRPR (Battery Remaining Percentage) to B1RP to match
the format of the other variables.
Change-Id: I64a744d78180156e16dbd483a35c7f97ac84bcba
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81406
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The BT1T (temperature) and BT1C (control) are not used so remove
them.
Change-Id: Ie6e85042ec59851bcfb4c88a2e04181c3c39f89c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81404
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The battery remaining percentage is a uint16_t, so correct this in
the EC memory. This change is non-function, as the EC is little
endian.
Change-Id: I56a0ae8199a95c9722e9bcb4c0739f4ef1d6ab05
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81403
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
