Utilize the new interrupt macros in order to specify correct
polarity of the gpio interupts. Some of the interrupts were
working by catching the opposite edge of the asserted interrupt.
BUG=chrome-os-partner:54977
Change-Id: I55bee2c4363cfdbf340a4d5b3574b34152e0069c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15646
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360727
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Utilize the new interrupt macros in order to specify correct
polarity of the gpio interupts. Some of the interrupts were
working by catching the opposite edge of the asserted interrupt.
BUG=chrome-os-partner:54977
BUG=None
BRANCH=None
TEST=None
Change-Id: Iee33c0a949be0a11147afad8a10a0caf6590ff7b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15645
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360726
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
FSP1_0 places romstage ram stack at fixed location of
RAMTOP in low memory before returning to coreboot proper.
There is no possibility of making a complete backup of
RAMBASE..RAMTOP region and currently such backup is not
even attempted.
As a conclusion, S3 resume would always cause OS memory
corruption.
BUG=None
BRANCH=None
TEST=None
Change-Id: I5b9dd4069082e022b01b0d6a9ad5dec28a06e8b0
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15576
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360723
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
In order to save power in S3, we remove reset gpio setting in kernel.
We still need to initialize touchscreen ic.
Do it by pulling low reset gpio for 500us and then pulling high
in firmware.
BRANCH=none
BUG=chrome-os-partner:55170
TEST=build on elm.
Change-Id: If2ac815c4fd5c5ae15443348a49eb31449b724b1
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/360312
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-by: Johnny Chuang <johnny.chuang@emc.com.tw>
Asserting this GPIO will send a signal to the EC to trigger a reset
for the AP and the CR50.
BRANCH=none
BUG=chrome-os-partner:55252
TEST=the device now reboots when it needs to switch between different
boot modes instead of hanging with "failed to reboot" message.
Change-Id: Idfd20977cf3682bd8933f89e8eec53005e55864e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360238
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The HTIF is deprecated and the newest RISC-V binutils don't know the
mtohost/mfromhost CSRs anymore.
The SBI implementation still needs to be restructured.
Change-Id: I13f01e45b714f1bd919e27b84aff8db772504b1f
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15289
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/360206
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch sets the devicetree for gpe0_dw configuration
and also configures the GPIO lines for SCI. EC_SCI_GPI
is configured to proper value.
BUG = chrome-os-partner:53438
TEST = Toggle pch_sci_l from ec console using gpioset command
and see that the sci counter increases in /sys/firmware/acpi/interrupt
and also 9 in /proc/interrupt
Change-Id: If258bece12768edb1e612c982514ce95c756c438
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15556
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360205
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
This patch sets the devicetree for gpe0_dw configuration
and also configures the GPIO lines for SCI. EC_SCI_GPI
is configured to proper value.
BUG = chrome-os-partner:53438
TEST = Toggle pch_sci_l from ec console using gpioset command
and see that the sci counter increases in /sys/firmware/acpi/interrupt
and also 9 in /proc/interrupt
Change-Id: I3ae9ef7c6a3c8688bcb6cb4c73f5618e7cde342c
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15325
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360204
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Bitmap images will be moved to CBFS from GBB. This patch adjust the flash
map accordingly for rambi, samus, peppy, parrot, falco, panther, auron,
strago.
BUG=chromium:622501
BRANCH=tot
TEST=emerge-{samus,falco} chromeos-bootimage
CQ-DEPEND=CL:354710,CL:355100
Change-Id: I0b82285186540aa27757e312e7bd02957f9962ec
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/355040
Specify the memory initialization parameters in
mainboard/intel/galileo/devicetree.cb. Pass these values into FSP to
initialize memory.
TEST=Build and run on Galileo Gen2
BUG=None
BRANCH=None
TEST=None
Change-Id: I83ee196f5fb825118a3a74b61f73f3728a1a1dc6
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15260
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/359317
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Switch the I2C scripts to properly match the I2C address selection for
the Galileo Gen1 board.
TEST=Build an run on Galileo Gen1
BUG=None
BRANCH=None
TEST=None
Change-Id: I9fc8b59a3a719abb474c99a83e0d538794626da9
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15258
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/359316
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Use the device driver for DA7219 device configuration in the SSDT and
remove the static copy in the DSDT.
Tested on reef to ensure that the generated SSDT contents are
equivalent to the current DSDT contents.
BUG=None
BRANCH=None
TEST=None
Change-Id: I288eb05d0cb3f5310c4dca4aa1eab5a029f216af
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15539
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/359311
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
IRQ 9 is used for different purpose on this board so move
SCI away to IRQ10.
BUG=None
BRANCH=None
TEST=None
Change-Id: I107bfb5ec8cd05f844ee75550779be7746e77a88
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/15563
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358957
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Based on the board revision apply the correct GPIO changes.
The only differences are the addition of 2 peripheral wake signals
and a dedicated peripheral reset line.
BUG=chrome-os-partner:54959,chrome-os-partner:54960,chrome-os-partner:54961
BRANCH=None
TEST=Built and tested on reef.
BUG=None
BRANCH=None
TEST=None
Change-Id: I9cac82158e70e0af1b454ec4581c2e4622b95b4b
Original-Signed-off-by: Aaron Durbin <adurbin@chromuim.org>
Original-Reviewed-on: https://review.coreboot.org/15562
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358897
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The board build version is provided by the EC on reef.
Provide the necessary functional support for coreboot
to differentiate the board versions.
BUG=chrome-os-partner:54959,chrome-os-partner:54960,chrome-os-partner:54961
BRANCH=None
TEST=Built and tested on reef.
BUG=None
BRANCH=None
TEST=None
Change-Id: I1b7e8b2f4142753cde736148ca9495bcc625f318
Original-Signed-off-by: Aaron Durbin <adurbin@chromuim.org>
Original-Reviewed-on: https://review.coreboot.org/15561
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358896
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
While the proto boards didn't have a memory SKU notion the
EVT boards do. Therefore, provide support for selecting the
proper memory SKU information based on the memory id straps.
This works on EVT boards because the pins used for the
strapping weren't used on proto. However, internal pullups
need to be enabled so that proto boards read the correct
id.
BUG=chrome-os-partner:54949
BRANCH=None
TEST=Built and used on reef for memory config.
BUG=None
BRANCH=None
TEST=None
Change-Id: I8653260e5d1b9adc83b78ea2770c683b72535e11
Original-Signed-off-by: Aaron Durbin <adurbin@chromuim.org>
Original-Reviewed-on: https://review.coreboot.org/15560
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358895
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
A call to early_mainboard_init is already present in verstage, thus it
is only necessary to call it from romstage when not in vboot context.
BUG=None
BRANCH=None
TEST=None
Change-Id: I2e0b5a369c5fb24efae4ac40d83a31f5cf4a078d
Original-Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/15450
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358837
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Since SPI controller opcode registers are locked by FSP, they need to be
initialized to a known good state before ReadyToBoot event and after
every SPI flash access (e.g. for MRC cache) has been finished in order
to enable the OS to use SPI controller without constraints.
BUG=None
BRANCH=None
TEST=None
Change-Id: I0a66344cd44e036c3999ae98d539072299cf5112
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/15547
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358832
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Enable the usage of DRIVER_INTEL_I210 and provide a function to search
for a valid MAC address for all i210 devices using hwilib.
BUG=None
BRANCH=None
TEST=None
Change-Id: Ic0f4f1579364cf5b0111334a05a8a0926785318b
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/15517
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358600
Reviewed-by: Martin Roth <martinroth@chromium.org>
The function mainboard_get_mac_address() is used to get a MAC address
for a given i210 PCI device. Instead of passing pure numbers for PCI
bus, device and function pass the device pointer to this function. In
this way the function can retrieve the needed values itself as well as
have the pointer to the device tree so that PCI path can be evaluated
there.
BUG=None
BRANCH=None
TEST=None
Change-Id: I2335d995651baa5e23a0448f5f32310dcd394f9b
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/15516
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358599
Reviewed-by: Martin Roth <martinroth@chromium.org>
Correct the GPP PCIe lane number comments so that they match the code.
BUG=None
BRANCH=None
TEST=None
Change-Id: If27c6a55ebedb0927dd9e8c7c9a833194e129a25
Original-Signed-off-by: Derek Waldner <derek.waldner.os@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15095
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358589
Reviewed-by: Martin Roth <martinroth@chromium.org>
Instantiate the touchpad using the drivers/i2c/generic device driver
to generate the ACPI object in the SSDT.
There is not currently a separate wake pin for this device, this will
be added in EVT hardware.
This was tested on the reef board by ensuring that the touchpad device
continues to work in the OS.
Also remove the LPC TPM from the DSDT as it is not present.
BUG=None
BRANCH=None
TEST=None
Change-Id: I3151a28f628e66f63033398d6fab9fd8f5dfc37b
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15481
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358583
Reviewed-by: Martin Roth <martinroth@chromium.org>
Gru and derivative boards use TPM2 to support Chrome OS verified boot.
BRANCH=none
BUG=chrome-os-partner:50645
TEST=re-built Kevin firmware, verified that TPM2 support over SPI is
enabled, and that with appropriate vboot and depthcharge patches
applied the device can boot into chrome os properly verifying RW
firmware and kernel key indices.
Change-Id: Ic6f3c15aa23e4972bf175b2629728a338c45e44c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354781
Reviewed-by: Shawn N <shawnn@chromium.org>
Add a few missing Kconfig defaults for derivatives of the Oak and Gru
baseboards. Also group all Kconfigs that must change for derivatives
together for easier updating.
BRANCH=None
BUG=None
TEST=None
Change-Id: I658130e88daa2d113fd722b0527cf0e7ab66c7ef
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/357922
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Updating so that ram id is read from adc instead of
hard-coded from config array. Also updated the
boardid readings so that they are bucketed instead
of within an error margin.
BRANCH=None
BUG=chrome-os-partner:54566,chrome-os-partner:53988
TEST=hexdump /proc/device-tree/firmware/coreboot/ram-code
and boardid when OS boots up. Also verified that
voltage read in debug output returns correct id.
Change-Id: I1c847558d54a0f7f9427904eeda853074ebb0e2e
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356584
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Enable reading of keyboard recovery host event
from coreboot.
BUG=None
BRANCH=None
TEST=esc+refresh+power combo and make sure you
see recovery fw screen.
Change-Id: Id980c77c8d7695b2c1b3343d968ad2a302d42aaa
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/357841
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Enabling CONFIG_EC_SOFTWARE_SYNC. Crossystem
needs this to get ec RW/RO info.
BUG=chrome-os-partner:54566
BRANCH=None
TEST=1. apreset from ec console. Check for
"VbEcSoftwareSync() check for RW update"
string in ap console.
2. Run "ectool version" from OS to check
that RO/RW version are different and
that we're in RW:
RO version: kevin_v1.1.4818-8243672
RW version: kevin_v1.1.4762-1957187
Firmware copy: RW
3. Run crossystem ecfw_act. check for
RW return value.
Change-Id: I0db8235cf7d472f0aa642eea1998282d010d3433
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/357811
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Add ACPI NHLT table generation that the current hardware
supports as well select the hardware used on the board.
Amenia has support for two audio codecs, Dialog for
headsets and Maxim for speakers.
Change-Id: Iaba9ec81ffb4f128f2e4413dec5174d9ecb856c9
Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Reviewed-on: https://review.coreboot.org/15024
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/357998
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
SD card need 20K PULLUP on D0-D3/CLOCK/COMMAND lines.
Without this SDCARD will throw data read/write errors.
BUG=chrome-os-partner:54676
TEST=Build and boot to OS.
Verify SD card is detected and data read/write works well.
Change-Id: I90da5b84dc2e488eb38f805322bd7b4dee394e5b
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://review.coreboot.org/15345
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/357661
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Configure unused Pads as NC
and sort the pads according to the gpio community.
Move the pad configurations from mainboard to gpio.h
BUG=none
TEST=Boot to OS and check all functionalities.
Change-Id: I8e9eeebf5d75c71c521649c72612c06f3fa43701
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/15327
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356740
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Declare the mainboard attached devices in the devicetree and enable
the provided device drivers by default to generate the ACPI objects
for these devices. Then remove the static ACPI objects from the DSDT
in mainboard.asl.
This was tesed on a Chell mainboard since I lack a kunitmisu device.
I used different GPIOs across boots to verify that the different
audio codec devices would be "detected" and generated in the SSDT.
Change-Id: I9b3b2247a84aeb7c07780958377d5bea14417ce6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15317
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/356450
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Declare the mainboard attached devices in the devicetree and enable
the provided device drivers by default to generate the ACPI objects
for these devices. Then remove the static ACPI objects from the DSDT
in mainboard.asl.
This was tested on a Chell mainboard since I lack a lars device.
Change-Id: Ifba6fc6589ddd54f4c85e8858f17997fbb4b6176
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15316
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/356449
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Declare the mainboard attached devices in the devicetree and enable
the provided device drivers by default to generate the ACPI objects
for these devices. Then remove the static ACPI objects from the DSDT
in mainboard.asl.
This was verified on a glados board by verifying the SSDT contents
against what used to be in the DSDT.
Change-Id: I710cbb8462d0fe695297102a64bec8e4212acc65
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15315
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/356448
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Declare the mainboard attached devices in the devicetree and enable
the provided device drivers by default to generate the ACPI objects
for these devices. Then remove the static ACPI objects from the DSDT
in mainboard.asl.
This was verified by comparing the generated ACPI code in the SSDT
to what was in mainboard.asl and ensuring the contents are
functionally equivalent.
Change-Id: I4725bbe2d47178568e3024fe3bb48cc80ff861c3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15314
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/356447
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
