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UPSTREAM: mainboard/google/reef: use new gpio interrupt macros

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Utilize the new interrupt macros in order to specify correct
polarity of the gpio interupts. Some of the interrupts were
working by catching the opposite edge of the asserted interrupt.

BUG=chrome-os-partner:54977

BUG=None
BRANCH=None
TEST=None

Change-Id: Iee33c0a949be0a11147afad8a10a0caf6590ff7b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15645
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360726
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Aaron Durbin 2016-07-12 17:17:21 -05:00 • committed by chrome-bot
commit e406ecbdb0
1 changed files with 14 additions and 14 deletions
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28
src/mainboard/google/reef/gpio.h
View file

@ -259,7 +259,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPIO_112, UP_20K, DEEP), /* SIO_SPI_1_FS0 */
PAD_CFG_GPI(GPIO_113, UP_20K, DEEP), /* SIO_SPI_1_FS1 */
/* Headset interrupt */
PAD_CFG_GPI_APIC(GPIO_116, NONE, DEEP, LEVEL, NONE), /* SIO_SPI_1_RXD */
PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP), /* SIO_SPI_1_RXD */
PAD_CFG_GPI(GPIO_117, UP_20K, DEEP), /* SIO_SPI_1_TXD */
/* SIO_SPI_2 -- unused */
@ -280,30 +280,30 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPIO_7, UP_20K, DEEP),
PAD_CFG_GPI(GPIO_8, UP_20K, DEEP),
PAD_CFG_GPI_APIC(GPIO_9, NONE, DEEP, LEVEL, NONE), /* dTPM IRQ */
PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP), /* dTPM IRQ */
PAD_CFG_GPI(GPIO_10, UP_20K, DEEP), /* unused */
PAD_CFG_GPI_SCI(GPIO_11, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC SCI */
PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE), /* EC SCI */
PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* unused */
PAD_CFG_GPI_APIC(GPIO_14, UP_20K, DEEP, LEVEL, NONE), /* FP IRQ */
PAD_CFG_GPI_APIC_LOW(GPIO_14, UP_20K, DEEP), /* FP IRQ */
PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* unused */
PAD_CFG_GPI_APIC(GPIO_18, NONE, DEEP, LEVEL, NONE), /* Trackpad IRQ */
PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP), /* Trackpad IRQ */
PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* unused */
PAD_CFG_GPI_APIC(GPIO_20, UP_20K, DEEP, LEVEL, NONE), /* NFC IRQ */
PAD_CFG_GPI_APIC(GPIO_21, NONE, DEEP, LEVEL, NONE), /* Touch IRQ */
PAD_CFG_GPI_SCI(GPIO_22, NONE, DEEP, LEVEL, NONE), /* EC wake */
PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP), /* NFC IRQ */
PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP), /* Touch IRQ */
PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, LEVEL), /* EC wake */
PAD_CFG_GPI(GPIO_23, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_24, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_25, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_26, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_27, UP_20K, DEEP), /* unused */
PAD_CFG_GPI_APIC(GPIO_28, NONE, DEEP, LEVEL, NONE), /* TPM IRQ */
PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */
PAD_CFG_GPO(GPIO_29, 1, DEEP), /* FP reset */
PAD_CFG_GPI_APIC(GPIO_30, NONE, DEEP, LEVEL, NONE), /* KB IRQ */
PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP), /* KB IRQ */
PAD_CFG_GPO(GPIO_31, 0, DEEP), /* NFC FW DL */
PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5), /* SUS_CLK2 */
PAD_CFG_GPI_APIC(GPIO_33, NONE, DEEP, LEVEL, NONE), /* PMIC IRQ */
PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP), /* PMIC IRQ */
PAD_CFG_GPI(GPIO_34, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_35, UP_20K, DEEP), /* unused */
PAD_CFG_GPO(GPIO_36, 0, DEEP), /* touch reset */
@ -321,7 +321,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */
PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* LPSS_UART2_TXD */
PAD_CFG_GPI(GPIO_48, UP_20K, DEEP), /* LPSS_UART2_RTS - unused */
PAD_CFG_GPI_SMI(GPIO_49, NONE, DEEP, LEVEL, NONE), /* LPSS_UART2_CTS - EC_SMI_L */
PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE), /* LPSS_UART2_CTS - EC_SMI_L */
/* Camera interface -- completely unused. */
PAD_CFG_GPI(GPIO_62, UP_20K, DEEP), /* GP_CAMERASB00 */
@ -361,8 +361,8 @@ static const struct pad_config proto_diff_table[] = {
/* Wake peripheral signals post proto. */
static const struct pad_config nonproto_diff_table[] = {
PAD_CFG_GPI_SCI(GPIO_3, UP_20K, DEEP, LEVEL, NONE), /* FP_INT_L */
PAD_CFG_GPI_SCI(GPIO_15, NONE, DEEP, LEVEL, NONE), /* TRACKPAD_INT_1V8_ODL */
PAD_CFG_GPI_SCI_LOW(GPIO_3, UP_20K, DEEP, LEVEL), /* FP_INT_L */
PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE), /* TRACKPAD_INT_1V8_ODL */
PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */
};