This patch extends `struct pad_config` to add new variable for gpio
lock action.
Additionally, it creates new GPIO PAD configuration macros that perform
GPIO pad configuration and pad lock configuration as well.
List of new macros are:
1. PAD_CFG_NF_LOCK
2. PAD_CFG_GPO_LOCK
3. PAD_CFG_GPI_LOCK
4. PAD_CFG_GPI_TRIG_OWN_LOCK
5. PAD_CFG_GPI_GPIO_DRIVER_LOCK
6. PAD_CFG_GPI_INT_LOCK
7. PAD_CFG_GPI_APIC_LOCK
8. PAD_CFG_GPI_IRQ_WAKE_LOCK
Mainboard users can use the above macros to lock the PAD after
configuration.
So far on IA chipset, the default GPIO pad lock configuration reset
type is POWERGOOD hence, it's recommended as per GPIO BWG (doc: 630603)
to configure the GPP PAD reset type the same as lock configuration
reset type to avoid GPP reset value misconfiguration issue.
BUG=b:211573253, b:211950520
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibf8b0a845005ad545266d995449d0aa711f45a61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch performs GPIO PAD lock configuration in non-smm mode.
Typically, coreboot enables SMI at latest boot phase post FSP-S,
hence, FSP-S might get chance to perform GPP lock configuration.
With this code changes, coreboot is able to perform GPIO PAD
lock configuration early in the boot flow, prior to calling FSP-S.
Also, this patch ensures to have two possible options as per GPIO
BWG to lock the GPIO PAD configuration.
1. Using SBI message with opcode 0x13
2. Using Private Configuration Register (PCR)
BUG=b:211573253, b:211950520
TEST=Able to build and boot brya variant with this code change.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I71b4e2f24303b6acb56debd581bd6bc818b6f926
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60801
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The TCO timer is the default watchdog of an x86 host and can reset the
system once it has expired for the second time. There are applications
where this reset is not acceptable while the TCO is used. In these
applications the TCO expire event generates an interrupt and software
takes care. There is a bit in the TCO1_CNT register on Elkhart Lake to
prevent this reset on expiration (called NO_REBOOT, see doc #636722 ).
This bit can either be strapped on hardware or set in this register to
avoid the reset on expiration. While the hardware strap cannot be
overridden in software, the pure software solution is more flexible.
Unfortunately, the location for this bit differs among the different
platforms. This is why it has to be handled on soc level rather than on
TCO common code level.
This commit adds a Kconfig option where NO_REBOOT can be enabled. This
makes it easy to reach this feature over to the mainboard where it can
be selected if needed.
Change-Id: Iaa81bfbe688edd717aa02db86f0a93fecdfcd16b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Since Tiger Lake platform, the HECI1 device can be disabled on
Alder Lake platform using two different mechanism:
A. Using PMC IPC command 0xA9.
B. Sending SBI message under SMM.
In current scope of Alder Lake the default implementation is using
(B) sending sbi message under SMM. A follow up patch to add the
possible options and let platform to choose the applicable one.
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
3. Default enable HECI1 device in `chipset.cb` to ensure the HECI1
device can undergo the PCI enumeration and later based on the
mainboard policy the HECI1 device can be disabled.
Mainboards that choose to make HECI1 enable during boot don't override
`DISABLE_HECI1_AT_PRE_BOOT` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enable PSE GBE with following changes:
1. Configure PCH GBE related FSP UPD flags
2. Add PSE GBE ACPI devices
3. Refactor PCH GBE FSP-S code and merge it together
with PSE GBE code
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: If3807ff5a4578be7b2c67064525fa5099950986a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The Intel® Programmable Services Engine (Intel® PSE) is a
dedicated offload engine for IoT functions powered by an ARM
Cortex-M7 microcontroller. It provides independent, low-DMIPS
computing and low-speed I/Os for IoT applications, plus
dedicated services for real-time computing and time-sensitive
synchronization.
The PSE hosts new functions, including remote out-of-band
device management, network proxy, embedded controller lite
and sensor hub.
This CL enables the user to provide the base address of the
PSE FW blob which will then be loaded by the FSP-S onto the
ARM controller. PSE FW will do the initialization work of
PSE controller and its peripherals. The loading of PSE FW
should have negligible impact on boot time unless PSE
controller could not locate the PSE FW and FSP will attempt to
redo PSE FW loading and wait for PSE handshake until it times
out. Once PSE controller locate the PSE FW, it will do
initialization concurrently by itself with coreboot booting.
It also adds PSE related FSP-S UPD settings which enable the
setup of peripheral ownership (assigned to the PSE or x86
subsystem) and interrupts. These assignments need to take
place at a given point in the boot process and cannot be
changed later.
To verify if PSE FW is loaded properly, the user could enable
PchPseShellEnabled flag and the log will be printed at PSE UART
2.
For further info please refer to doc #611825 (for HW overview)
and #614110 (for PSE EDS).
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
When calling get_pcie_rp_pmc_idx(), the following code checked the
return value to see if it was negative or `> CONFIG_MAX_ROOT_PORTS`.
However, the expected return value for CPU PCIe RPs is above
MAX_ROOT_PORTS. Since the static, local function is intended to return
-1 or a valid value, drop the check for `> CONFIG_MAX_ROOT_PORTS`.
Change-Id: I2039273ad246884cd8736a7f0355e621a706a526
Fixes: b6a15a7 ("soc/intel/common/block/pcie/rtd3: Update ACPI Update
ACPI methods for CPU PCIe RPs")
Tested-by: Tim Crawford <tcrawford@system76.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
The patch implements get_soc_cpu_type() helper function which
determines whether the executing CPU is a small or a big core. This is
the SoC-specific callback that must be implemented for SoCs that select
SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID. It will be called from
set_cpu_type().
TEST=verified on Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Icd0d7e8a42c4b20d3e1d34998bca6321509df2d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This command retrieves a set of boot performance timestamps
CSME collected during the platform's last boot flow.
BUG=b:182575295
TEST=Verify CSME timestamps after S3 and boot.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ic6f7962c49b38d458680d51ee1cd709805f73b66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch provides the possible options for PCH to allow `Pad
Configuration Lock`.
`SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI` config is for Tiger Lake
Point (TGP) and Alder Lake Point (ADP) PCH.
BUG=b:211573253, b:211950520
TEST=None
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7cf35893ab613b154a1073060081a09e561ffe56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch introduces a `const bit_mask` variable to hold the gpio
PAD mask value prior to sending the lock configuration command using
the sideband interface.
Additionally, this patch fixes the PAD lock overridden issue as below:
Without this code change every consecutive PAD lock operation resets
other bits in that register as below:
After Locking pad 2 , pcr_read=0x4
After Locking pad 3 , pcr_read=0x8
After Locking pad 4 , pcr_read=0x10
After Locking pad 5 , pcr_read=0x20
After Locking pad 6 , pcr_read=0x40
After Locking pad 7 , pcr_read=0x80
After Locking pad 8 , pcr_read=0x100
With this code change all previous lock bits are getting preserved as
below:
After Locking pad 2 , pcr_read=0x4
After Locking pad 3 , pcr_read=0xc
After Locking pad 4 , pcr_read=0x1c
After Locking pad 5 , pcr_read=0x3c
After Locking pad 6 , pcr_read=0x7c
After Locking pad 7 , pcr_read=0xfc
After Locking pad 8 , pcr_read=0x1fc
BUG=b:211573253, b:211950520
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I342a666aa2d34bcc8ba33460396d1248f0c0f89f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60999
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ADL-P 2+8+2 (28W) would have a match PD to ADL-P 4+8+2 (28W). Group them
into the same group core "ADL_P_282_482_28W_CORE".
BUG=b:211365920
TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: I3f92c0f5d717dd33ac478fbaa883f3e972e7a7de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The only option to make HECI1 function disable on Elkhart Lake SoC
platform is using SBI under SMM mode.
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I76c625e6221fdef1343599e7dbc7739caa91bf98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
The only option to make HECI1 function disable on Ice Lake SoC
platform is using SBI under SMM mode. Hence, this patch makes
DISABLE_HECI1_AT_PRE_BOOT=y default and selects
`HECI_DISABLE_USING_SMM` config for Ice Lake.
Also, drop `HeciEnabled` from chip configuration and guard
heci_disable() using DISABLE_HECI1_AT_PRE_BOOT config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If4155e5c7eeb019f7dce59acd5b82720baddcb43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
set_cpu_type(): It determines the CPU type (big or small) that
is executing the function, and marks the global_cpu_type's array slot
which is corresponds to the executing CPU's index if the CPU type is
big core.
get_cpu_index(): It determines the index from LAPIC Ids. This is
required to expose CPPC3 package in ascending order of CPUs' LAPIC ids.
So, the function returns CPU's position from the ascending order list
of LAPIC ids.
TEST=Tested CPU index calculation, core type determination on Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If4ceb24d9bb1e808750bf618c29b2b9ea6d4191b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch implements a SoC overrides to check CPU privilege level
as the MSR is not consistent across platforms.
For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR
0x151.
BUG=b:211573253, b:211950520
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I515f0a3548bc5d6250e30f963d46f28f3c1b90b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch creates a `relative increment by 1` macro to let SoC
gpio pad configuration to be more flexible while adding support
for newer PCH SoC.
With this changes adding GPIO controller support for PCH-N would
become really simple without too much of code duplication.
For example: ADL-N has added `GPP_I` pins into community 1 hence,
the additional code for `PCH-N` whould appear incremetal to ADL-P.
> #define GPP_B 0x0
> #define GPP_T INC(GPP_B)
> #define GPP_A INC(GPP_T)
> #define GPP_R INC(GPP_A)
> #define GPD INC(GPP_R)
> #define GPP_S INC(GPD)
> if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
> #define GPP_I INC(GPP_S)
> #define GPP_H INC(GPP_I)
> #else
> #define GPP_H INC(GPP_S)
> #endif
> #define GPP_D INC(GPP_H)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie3b2183381b877da0a6e5a27f5176f0e21e0c9fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Add eMMC device into chipset.cb and keep it `off` by default.
eMMC device is applicable only for Alder Lake N SOC.
Change-Id: I2bc38ee5814688409feb7e4531c1daa5b54953c0
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Host device id 0x4619 is missed in few coreboot tables so that
coreboot can't recognize and config it properly.
Document Number: 690222
BUG🅱️214665785, b:214680767
Change-Id: I95908bdc0a736bafedb328dda2a00b5473de3d88
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Cannon Lake
and ensures disable_heci1() is guarded against this config.
Also, makes dt CSE PCI device `on` by default.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Idd57d2713fe83de5fb93e399734414ca99977d0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch checks if CSE's spi protection mode is protected or
unprotected. Returns true if CSE's spi protection mode is protected,
otherwise false.
BUG=b:211954778
TEST=Able to build and boot brya with this change. Calling
`cse_is_hfs1_spi_protected()` in coreboot is able to provide
the SPI protection status.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I23f1a1c4b55d8da6e6fd0cf84bef86f49ce80cca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
3. Make dt CSE PCI device `on` by default.
4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1
function disable at pre-boot instead of the dt policy that uses
`HeciEnabled = 0`.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The existing Sideband access is with the PCH P2SB. There will be future
platforms which access the TCSS registers through SBI other than the PCH
P2SB. This change abstracts the SBI with common API.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia6201762fe92801ce6b4ed97d0eac23ac71ccd37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change adds the Primary to Sideband Bridge(B0, D31, F1)
definition for the platform in order to maintain the common block
API build.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I1c4ddfce6cc6e41b2c63f99990d105b4bbb6f175
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4a81fd58df468e2711108a3243bf116e02986316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI
bit set for any slots of already existing boards, add set the option
PcieRpSlotImplemented=1 where appropriate.
Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Make use of the helper introduced in the parent change to deduplicate
the PCIe root port table.
Change-Id: I2dae4e4caf0a7ba3662889f3b31da0c3c299bc92
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add TGL-H support for the recently introduced code for differentiating
CPU and PCH root ports by adding the missing TGL-H port map.
Change-Id: Id2911cddeb97d6c164662e2bef4fdeece10332a8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The headers added are generated as per FSP v2511_04
Previous FSP version was v2471_02
Changes include:
- UPDs description update in FspsUpd.h and FspmUpd.h
- Adjust UPD Offset in FspmUpd.h
- Name change of UPDs in FspmUpd.h and FspsUpd.h
- Copyright year is updated in FspmUpd.h and FspsUpd.h
- Updated spd_upds and dq_upds structure variables in meminit.c
- Updated structure member of s_cfg->LpmStateEnableMask to PmcLpmS0ixSubStateEnableMask
in fsp_params.c
BUG=b:213959910
BRANCH=None
TEST=Build and boot brya
Cq-Depend: chrome-internal:4448696, chrome-internal:4445910
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com>
Change-Id: I39646c6812afbf622171361b8206daeacdaafac0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Currently coreboot and EC had different logic to interpret TCSS port
number which would break retimer update functionality since coreboot
would pass wrong port information to EC.
This change clones the implementation on Alder Lake which converts
the phyiscal port mapping to EC's abstract port mapping.
BUG=b:207057940
BRANCH=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: If4451598dbb83528ae6d88dbc1b65c206f24fe1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
TGL-LP only has 12 root ports, not 20. Correct the port map.
Change-Id: I3f5c69a2e7e3a2b8292c81beeac4ea6c7279d4b4
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Apollo Lake
and ensures disable_heci1() is guarded against this config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7ac0cad97fcd42b2c6386693319d863352356864
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Move the `configure_pmc_descriptor()` function to SoC scope instead of
having two identical copies in mainboard scope. Add a Kconfig option to
allow mainboards to decide whether to implement this workaround.
Change-Id: Ib99073d8da91a93fae9c0cebdfd73e39456cdaa8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch migrates common code API into SoC specific implementation
to drop CPU privilege level as the MSR is not consistent across
platforms.
For example: On APL/GLK, it's MSR 0x120 and CNL onwards it's MSR 0x151.
Also, include `soc/msr.h` in cpu.h to fix the compilation issue.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0b6f39509cc5457089cc15f28956833c36b567ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60898
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a config to let mainboard users choose the correct
state of HECI1(CSE) device prior to handing off to payload.
`DISABLE_HECI1_AT_PRE_BOOT` config to make HECI1 function disable
at pre-boot.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7e127816c506df3ac0cf973b69021d02d05bef4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We support all the ADL-P 15W/28W/45W SKU's and map them with the
latest VR configurations. These config values are generated by iPDG
application with ADL-P platform package tool.
RDC Kit ID for the iPDG tools
* Intel(R) Platform Design Studio Installer: 610905
* Intel(R) Platform Design Studio - Libraries: 613643
* Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345
* Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261
BUG=b:211365920
TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: Ida7a6df0422a9a3972646cb3bdd0112b5efa2755
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Enable CPPC entries generation, needed for Intel SpeedShift.
This can be tested by checking sysfs in Linux:
$ grep . /sys/devices/system/cpu/cpu?/acpi_cppc/*perf
The output should look like this, while the values may differ:
/sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf:28
/sys/devices/system/cpu/cpu0/acpi_cppc/lowest_nonlinear_perf:5
/sys/devices/system/cpu/cpu0/acpi_cppc/lowest_perf:1
/sys/devices/system/cpu/cpu0/acpi_cppc/nominal_perf:24
/sys/devices/system/cpu/cpu1/acpi_cppc/highest_perf:28
/sys/devices/system/cpu/cpu1/acpi_cppc/lowest_nonlinear_perf:5
...
Change-Id: I910b4e17d4044f1bf1ecfa0643ac62fc7a8cb51b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
FSP reserved memory is allocated inside cbmem which already gets
marked as a reserved memory region, so there is no need to do this
explicitly.
Change-Id: I39ec70bd9404d7bc2a4228c4364e4cc86f95d7c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
The PMC IPC method that is used for RTD3 support expects to be provided
the virtual wire index instead of the LCAP PN for CPU PCIe RPs.
Therefore, use the prior patches to update pcie_rp for CPU RPs.
Note that an unused argument to pcie_rtd3_acpi_method_status() was also
dropped.
BUG=b:197983574
TEST=add rtd3 node under pcie4_0 in overridetree for brya0, boot and
inspect the SSDT to see the PMC IPC parameters are as expected for the
CPU RP, and the ModPhy power gating code is not found in the AML for the
PEG port.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I84a1affb32cb53e686dbe825d3c3a424715df873
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60183
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Alder Lake chip.h file has pcie_rp_config entries for the CPU PCIe
ports, but the UPDs are not set. This patch hooks up those config
structs to the appropriate FSP-S UPDs.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ibb2375e66d53b4b7567dbe88b941cd720fdad927
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
When using a mixed memory topology with DDR4, it's not possible to boot
when no DIMMs are installed, even though memory-down is available. This
happens because the DIMM SPD length defaults to 256 when no DIMM SPD is
available. Relax the length check when no DIMMs are present to overcome
this problem.
Tested on system76/lemp10. Unit boots with and without DIMM installed.
Change-Id: I1cabf64fade1c06a44b6c3892659d54febc7a79a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
