mtrr_use_temp_range() is used to temporarily cache the area(s) of RAM
to which the SPI flash is mapped, in order to speed up reading the
payload out of flash in preparation for execution. On systems with more
than 32GiB of RAM, there are not enough MTRRs available to map the
"permanent" regions below 4GiB, these temporary regions below 4GiB, and
any RAM above 4GiB due to fragmentation in the various ranges, as well
as limitations on the area covered by a single MTRR due to how they
are stored in the CPU registers.
As a workaround, if the number of MTRRs needed for the temporary map
exceeds the maximum available for the system, retry calc_var-mtrrs()
with `above4gb` set to false.
TEST=build/boot starlabs/starbook_mtl with > 32GB RAM, verify temporary
MTRRs are able to be assigned via cbmem console log, and no boot delays
in payload loading/decompression due to the SPI flash not being cached.
Change-Id: Ia9f9a1537e7e0c2f7ce21067eceb1549d0f9ea5b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
calc_var_mtrrs() calculates the number of MTRRs needed for both WB and
UC default memory types, and returns the type that uses fewer MTRRs.
Modify it to return the number of MTRRs used as well, and if that
count exceeeds the number available on the system, throw an error
and skip calling prepare_var_mtrrs() as we know it will fail.
TEST=tested with rest of patch train
Change-Id: I2be7c5b3385731f4dc9ef62de15dcf6d4cceb5d3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86955
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No need for this to be a signed or unsigned int.
TEST=tested with rest of patch train.
Change-Id: I409c04b928211e0e89eec324fdf3fa3997c73576
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86942
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On AMD platforms the SPI flash can be accessed using the ROM3
mapping in upper MMIO space. To reach the MMIO window the default
page tables must be extended to cover the address by default.
Add support for a SoC specific default address space being used on
x86_64, where the default of 4GiB/512GiB remains.
The size can be specified by the Kconfig CPU_PT_ROM_MAP_GB option.
Used in the following patch to use ROM3 mapping on AMD platforms.
TEST: Access ROM3 bar at 0xfd00000000 on amd/birman+ using x86_64
TEST: x86_64 still works on qemu/q35.
Change-Id: If669426f2b5ae40dd5c62e17f3a0234783b7d462
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
The x86 (AMD and Intel) spec defines it as Page-Map Level-4 Entry.
It is annoying when searching for the wrong abbreviation in the spec so
fix it everywhere it occurs.
source: Intel 64 spec April 2022 and AMD64 spec April 2024.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I730235beea69b3720f080bbade083c2eeed26587
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86587
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
The smm_get_save_state() function returns an invalid pointer (negative
pointer) when the cpu variable is equal to the number of CPUs. This
leads to a hang when the pointer is used to access the save state.
TEST=No unexpected hangs in System Management Mode (SMM) were detected
on fatcat.
Change-Id: I09f969105190a004372c43cb1542f5b716da1eda
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
This resolves a crash issue observed on Meteor Lake and introduced by
commit 70bdd2e1fa ("cpu/x86/topology:
Simplify CPU topology initialization"). This commit simplifies the
code and provides more detailed CPU topology information by
generalizing the use of the Extended Topology Enumeration Leaves
0x1f. As a result, the coreboot APIC core_id field does not provide
the fully detailed path information.
It turns out that the topology core identifier is used by the coreboot
MP service mp_get_processor_info() implementation. But the MP Service
EFI_CPU_PHYSICAL_LOCATION data structure only captures information
about the package, core, and thread. The core identifier returned to
the MP service caller must incorporate the full hierarchical path (die
group, die, module, tile, module and core).
This commit adds a new field to the cpu topology structure to
represent the core ID within the package.
For reference, here is that signature of the crash:
LAPIC 0x40 in X2APIC mode.
CPU Index 2 - APIC 64 Unexpected Exception:13 @ 10:69f3d1e4 - Halting
Code: 0 eflags: 00010046 cr2: 00000000
eax: 00000001 ebx: 69f313e8 ecx: 0000004e edx: 00000000
edi: 69f38018 esi: 00000029 ebp: 69aeee0c esp: 69aeedc0
[...]
The crash occurred when FSP attempted to lock the Protected
Processor Inventory Number Enable Control MSR (IA32_PPIN_CTL
0x4e).
69f3d1d3: 8b 43 f4 mov -0xc(%ebx),%eax
69f3d1d6: 89 4d c4 mov %ecx,-0x3c(%ebp)
69f3d1d9: 89 45 dc mov %eax,-0x24(%ebp)
69f3d1dc: 8b 55 c4 mov -0x3c(%ebp),%edx
69f3d1df: 8b 45 c0 mov -0x40(%ebp),%eax
69f3d1e2: 8b 4d dc mov -0x24(%ebp),%ecx
69f3d1e5: 0f 30 wrmsr
69f3d1e7: e9 ee fd ff ff jmp 0xfffffe39
FSP experiences issues due to attempting to lock the same register
multiple times for a single core. This is caused by an inconsistency
in the processor information data structure, where multiple cores
share the same identifier. This is not permitted and triggers a
General Protection Fault Exception.
TEST=Executing CpuFeaturesPei.efi in FSP-S does not crash on a rex
board.
Change-Id: I06db580cddaeaf5c452fa72f131d37d10dbc5974
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86004
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Store CR3 on stack and restore it when returning from protected
mode call, since the stage might have set up different page tables
than the default ones linked into all stages.
Tested: intel/archercity still boots to payload in x86_64.
Change-Id: If94a24925994ac9599be24f6454ea28d02ff0c67
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
FSP, that is build against EDK2 2018 or newer, is able to back up and
restore the bootloader IDT on entry/exit. Even though it sets up its
own IDT, FSP checks the bootloader IDT size and deadloops without
warning if it's too big.
On x86_64 coreboot the IDT is naturally bigger than on x86_32 and thus
x86_32 FSP might die on entry. Work around this issue by:
* Back up and restore the IDT in protected_mode_call_wrapper
* Load zero IDT in protected mode before jumping to function
TEST: Can boot on SPR FSP (x86_32) using x86_64 coreboot with
exceptions in romstage enabled.
Change-Id: I56367d8153aa10a9b1bcaa5ffde8ebe202e8c00c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85789
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This commit adds a module_id field to the cpu_topology structure.
This field is used to identify the module that a CPU is located
on. This information is useful for power management and other
purposes.
Change-Id: I1c8a76dce48c0539a3f36015674553a2461dec27
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85577
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit rewrites the CPU topology initialization code to simplify
it and make it more maintainable.
The previous code used a complex set of if-else statements to
initialize the CPU topology based on the CPUID leaves that were
supported. This has been replaced with a simpler and more readable
function that follows the Intel Software Developer Manual
recommendation by prioritizing CPUID EAX=0x1f over CPUID EAX=0xb if
available.
The new code removes the need for separate functions to handle the
topology initialization for different CPUID leaves. It uses a static
array of bitfield descriptors to store the APIC ID descriptor
information for each level of the CPU topology. This simplifies the
code and makes it easier to add new levels of topology in the future.
The code populates the node ID based on the package ID, eliminating
the need for an extra function call.
Change-Id: Ie9424559f895af69e79c36b919e80af803861148
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85576
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
PRMRR (Protected Region Memory Range Region) are not accessible as
normal DRAM regions and needs to be explicitly reserved in memory
map.
Change-Id: I81d17b1376459510f7c0d43ba4b519b1f2bd3e1f
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Definitions of __fls/__ffs from lib.h and fms/fls from
cpu/x86/mtrr.h are duplicated. Use definition from lib.h which is
more generic.
Change-Id: Ic9c6f1027447b04627d7f21d777cbea142588093
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Suggested-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85104
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GCC LTO incorrectly warns about this it seems.
This also exits gracefully from stage-cache code if no smm region is
found.
Change-Id: Ib1851295646258e97c489dc7402b9df3fcf092c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84040
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For LTO we want to link everything in one go.
Change-Id: If2c186eb87072e0b80c7e8998b2a0d9bdfddf740
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84037
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When clang supports linking bare metal targets it defaults to LLD for
linking which linking those raw data structures used to generate CBFS
page tables does not fare well.
Change-Id: I66fb374a456ea752a97a41426c5a98e6747f3a92
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The current region_end() implementation is susceptible to overflow
if the region is at the end of the addressable space. A common case
with the memory-mapped flash of x86 directly below the 32-bit limit.
Note: This patch also changes console output to inclusive limits.
IMO, to the better.
Change-Id: Ic4bd6eced638745b7e845504da74542e4220554a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
We introduce two new functions to create region objects. They allow us
to check for integer overflows (region_create_untrusted()) or assert
their absence (region_create()).
This fixes potential overflows in region_overlap() checks in SMI
handlers, where we would wrongfully report MMIO as *not* overlapping
SMRAM.
Also, two cases of strtol() in parse_region() (cbfstool), where the
results were implicitly converted to `size_t`, are replaced with the
unsigned strtoul().
FIT payload support is left out, as it doesn't use the region API
(only the struct).
Change-Id: I4ae3e6274c981c9ab4fb1263c2a72fa68ef1c32b
Ticket: https://ticket.coreboot.org/issues/522
Found-by: Vadim Zaliva <lord@digamma.ai>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit fixes an incorrect variable name in the page table setup
for 1 GiB pages.
The label PDE_table was used when it should have been PDPT, as it
represents a "Page Directory Pointer Table (PDPT)", not a "Page
Directory Table (PDT) or PDE_Table".
This change ensures correct nomenclature and consistency in the code.
PML4 -> PDPT --------> 1GB Physical Page
As per x86-64 specification, 1GB pages bypass the Page Directory Table
(PDT) level of the page table hierarchy, mapping directly from the
Page Directory Pointer (PDPT) Table to the physical page.
Change-Id: I1e1064653a265215054f31f0e4e46bf8200ca471
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83100
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This patch flips the polarity of CONFIG_USE_1G_PAGES_TLB into
CONFIG_NEED_SMALL_2MB_PAGE_TABLES which is off by default, meaning
CPUs added in the future will automatically build the smaller 1GB pages.
We can expect support for this feature to be available on all future CPU
generations (with the possible exception of embedded edge cases), so
this default setting should make mistakes less likely and keep
maintenance effort lower. (Besides, enabling the support where it
doesn't work fails fast, whereas keeping it disabled where it could work
is an inefficiency that can easily go overlooked for a long time.)
While this is technically a CPU feature, not a northbridge feature, we
support a lot more individual CPUs than northbridges in the pre-SoC era,
and they tend to be closely coupled anyway. So select the option at the
northbridge level for older CPUs to keep things simpler.
Change-Id: I2cf1237a7fb63b8904c2a3d57fead162c66bacde
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Code dealing with PAE can be used outside of memset_pae(). This change
extracts creation of identity mapped pagetables to init_pae_pagetables()
and mapping of single 2 MiB map to pae_map_2M_page(). Both functions are
exported in include/cpu/x86/pae.h to allow use outside of pgtbl.c.
MEMSET_PAE_* macros were renamed to PAE_* since they no longer apply
only to memset_pae().
Change-Id: I8aa80eb246ff0e77e1f51d71933d3d00ab75aaeb
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82249
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
<stdio.h> header is used for input/output operations (such as printf,
scanf, fopen, etc.). Although some input/output functions can manipulate
strings, they do not need to directly include <string.h> because they
are declared independently.
Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This function had roughly the same use (except PAT) as part of
memset_pae(), however the latter is able to make use of PAE and map
physical memory located above 4 GB. Remove paging_identity_map_addr()
to avoid semi-duplicated code.
The function has been unused since CB:26745.
Change-Id: I7a4ebd84a6f5d222c3b2c6c6e3d26d6464cf01b8
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82248
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This function isn't used anywhere. It probably wouldn't work with
current coreboot anyway, as it identity mapped lower 2GB of RAM, while
ramstage is run from CBMEM, which is usually just below top of memory.
It was last used in K8 code that is long gone.
Change-Id: I97e2830f381181d7f21ab5f6d4c544066c15b08c
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
<string.h> is supposed to provide <stdarg.h> and <stdio.h>
Change-Id: I021ba535ba5ec683021c4dfc41ac18d9cebbcfd2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81853
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
<device/device.h> is supposed to provide <device/{path,resource}.h>
Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This removes the runtime SMI call to set up the communication buffer
for SMMSTORE in favor of setting this buffer up during the installation
of the smihandler.
The reason is that it's less code in the handler and a time costly SMI
is also avoided in ramstage.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I94dce77711f37f87033530f5ae48cb850a39341b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Currently the SRAT table only exposes one proximity group as
it uses the LAPIC node_id, which is always initialized to 0.
Use CPUID leaf 0x1f or 0xb to gather the node ID and fill it
to make sure that at least one proximity group for every socket
is advertised.
For now the SNC config isn't taken into account.
Change-Id: Ia3ed1e5923aa18ca7619b32cde491fdb4da0fa0d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
When switching back and forth between 32 to 64 bit mode, for example to
call a 32-bits FSP or to call the payload, new page tables in the
respective stage will be linked.
The advantages of this approach are:
- No need to determine a good place for page tables in CBFS that does
not overlap.
- Works with non memory mapped flash (however all coreboot targets
currently do support this)
- If later stages can use their own page tables which fits better with
the vboot RO/RW flow
A disadvantage is that it increases the stage size. This could be
improved upon by using 1G pages and generating the pages at runtime.
Note: qemu cannot have the page tables in the RO boot medium and needs
to relocate them at runtime. This is why keeping the existing code with
page tables in CBFS is done for now.
TEST: Booted to payload on google/vilbox and qemu/q35
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80337
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This data is used by smm_region_overlaps_handler(). Callers use this
helper to determine if it's safe to read/write to memory buffers taken
from untrusted input.
coreboot SMI handlers must not be confused into writing over any SMRAM
subregion, which includes the TSEG_STAGE_CACHE and chipset-specific area
(sometimes, IED), not just the handlers.
If stage cache writes were permitted, this could compromise the
integrity of the S3 resume path.
The consequences to overwriting the chipset-specific area are undefined.
Change-Id: Ibd9ed34fcfd77a4236b5cf122747a6718ce9c91f
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80703
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The commit below uses USE_1G_PAGETABLES config flag instead of
the correct USE_1G_PAGES_TLB.
"commit ecbc243a45
("cpu/x86: Add 1GiB pages for memory access up to 512GiB")"
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ic19812bc1f90cbe7d3739c42a0314b3650e0501d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Improves user experience by highlighting a possibility of runtime
hangs caused by unsupported WB caching during NEM.
Recently we have encountered an issue on Intel platform and came to
know about the NEM logical limitation where due to cache sets are not
in power_on_two running into a runtime hang upon enabling WB caching.
BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot on google/ovis and google/rex (including Ovis with
non-power-of-two cache configuration).
Change-Id: Ic4fbef1fcc018856420428139683897634c9f85d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81336
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Relying on page tables being in RO flash is not safe in every setup,
therefore set up some page tables in SMRAM that the permanent smihandler
can use.
Tested on QEMU.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Icb3086abd577b9abb9966dd910a264a873ace4ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80336
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To allow for more flexibility like generating page tables at runtime or
page tables that are part of the ramstage, add a parameter to
sipi_vector.S and smm_stub.S so that APs use the same page tables as the
BSP during their initialization.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I1250ea6f63c65228178ee66e06d988dadfcc2a37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80335
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
No rmodule was using heap.
Change-Id: I0bc049a5231dabbec1c962a99ef875eddcc4ac6e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This makes it easier to reuse, e.g. if you want to do it twice in one
assembly file.
Change-Id: Ida861338004187e4e714be41e17c8447fa4cf935
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Current pagetable implementation allows memory access up to 4GiB using
2MiB pages. If user wants to access more than 4GiB with a 2MiB page it
will require more pagetable entries. By using a 1GiB page table, users
can access more than 4GiB of memory while reducing the number of
pagetable entries. This patch enables memory access up to 512GiB through
1GiB pages by selecting USE_1G_PAGES_TLB in Kconfig.
TEST: Verified in 64bit mode boot and access above 4GiB
Change-Id: Id569ae5b50abf5b72e4db33b5e4cd802399e76ec
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80088
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
When a device with no resource is passed it will keep overwriting
the current slot. Remove the conditional and allow a PCI device
to not have any resources.
This is particular useful for the next commits that makes use
of the PCI resource store to pass UBOX devices to SMM that allow
to lock-down SMM from within an SMI handler. Those devices do
not have any resources and cannot be hardcoded in SMM as their
PCI segment group and bus number varies depending on socket
count, CPU discovery and configuration.
Change-Id: I1a1b5944c97da5be6b9794c653b5159683f492e5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80246
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Allow SMM to verify the list of provided PCI devices by comparing
the device and vendor ID for each PCI device.
Change-Id: I7086fa450fcb117ef8767c199c30462c1ab1e1b6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.
This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I552d487978906f5ea74c3d0d85373fe5b2de3f38
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80068
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Always use the high-level API region_offset() and region_sz()
functions. This excludes the internal `region.c` code as well
as unit tests. FIT payload support was also skipped, as it
seems it never tried to use the API and would need a bigger
overhaul.
Change-Id: Iaae116a1ab2da3b2ea2a5ebcd0c300b238582834
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79904
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Use call_smm instead of writing the command number directly to the APMC
SMI command IO port.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iefbdb3d17932d6db6a17b5771436ede220c714fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79828
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Even though the return value from apm_control isn't checked at any of
its call sites, using the cb_err enum instead of an integer as return
type makes it clearer what the returned value means.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I07ced74cae915df52a9d439835b84237d51fdd11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79835
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Instead of hard-coding the APMC SMI command IO port in the FADT, call
pm_acpi_smi_cmd_port() to get the APMC SMI command IO port. Also update
the comment in apm_get_apmc to match what it's doing.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0f36b8a0e93a82b8c6d23c5c5d8fbebb1bc6b0bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
