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cpu/x86/64bit: Turn jumping to long mode into a macro

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This makes it easier to reuse, e.g. if you want to do it twice in one
assembly file.

Change-Id: Ida861338004187e4e714be41e17c8447fa4cf935
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans 2021-07-05 21:18:50 +02:00 • committed by Felix Held
commit 3edf840ad1
11 changed files with 30 additions and 19 deletions
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4
src/cpu/intel/car/core2/cache_as_ram.S
View file

@ -4,6 +4,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
#include <cpu/x86/64bit/entry64.inc>
.section .init
.global bootblock_pre_c_entry
@ -162,8 +163,7 @@ addrsize_set_high:
subl $4, %esp
#if ENV_X86_64
#include <cpu/x86/64bit/entry64.inc>
setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
movd %mm2, %rdi
shlq $32, %rdi

4
src/cpu/intel/car/non-evict/cache_as_ram.S
View file

@ -4,6 +4,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
#include <cpu/x86/64bit/entry64.inc>
#define NoEvictMod_MSR 0x2e0
#define BBL_CR_CTL3_MSR 0x11e
@ -213,8 +214,7 @@ end_microcode_update:
andl $0xfffffff0, %esp
#if ENV_X86_64
#include <cpu/x86/64bit/entry64.inc>
setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
movd %mm2, %rdi
shlq $32, %rdi

3
src/cpu/intel/car/p4-netburst/cache_as_ram.S
View file

@ -13,6 +13,7 @@
.global bootblock_pre_c_entry
#include <cpu/intel/car/cache_as_ram_symbols.inc>
#include <cpu/x86/64bit/entry64.inc>
.code32
_cache_as_ram_setup:
@ -362,7 +363,7 @@ fill_cache:
subl $4, %esp
#if ENV_X86_64
#include <cpu/x86/64bit/entry64.inc>
setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
movd %mm2, %rdi
shlq $32, %rdi /* BIST */

3
src/cpu/qemu-x86/cache_as_ram_bootblock.S
View file

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <cpu/x86/post_code.h>
#include <cpu/x86/64bit/entry64.inc>
#define CBFS_FILE_MAGIC 0
#define CBFS_FILE_LEN (CBFS_FILE_MAGIC + 8)
@ -79,7 +80,7 @@ pages_done:
#if ENV_X86_64
/* entry64.inc preserves ebx. */
#include <cpu/x86/64bit/entry64.inc>
setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
/* Restore the BIST result and timestamps. */
movd %mm2, %rdi

12
src/cpu/x86/64bit/entry64.inc
View file

@ -22,10 +22,9 @@
#include <arch/rom_segs.h>
#endif
setup_longmode:
.macro setup_longmode page_table
/* Get page table address */
movl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %eax
movl \page_table, %eax
/* load identity mapped page tables */
movl %eax, %cr3
@ -48,12 +47,13 @@ setup_longmode:
/* use long jump to switch to 64-bit code segment */
#if defined(__RAMSTAGE__)
ljmp $RAM_CODE_SEG64, $__longmode_start
ljmp $RAM_CODE_SEG64, $jmp_addr\@
#else
ljmp $ROM_CODE_SEG64, $__longmode_start
ljmp $ROM_CODE_SEG64, $jmp_addr\@
#endif
.code64
__longmode_start:
jmp_addr\@:
.endm
#endif

5
src/cpu/x86/64bit/mode_switch.S
View file

@ -1,4 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <cpu/x86/64bit/entry64.inc>
/* Calls a x86_32 function from x86_64 context */
.text
@ -42,8 +43,8 @@ protected_mode_call_wrapper:
call *%ebx
movl %eax, %ebx
/* Jump to long mode. Preserves ebx */
#include <cpu/x86/64bit/entry64.inc>
/* Preserves ebx */
setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
/* Place return value in rax */
movl %ebx, %eax

4
src/cpu/x86/64bit/mode_switch2.S
View file

@ -4,6 +4,8 @@
* Must not be directly invoked from C code!
*/
#include <cpu/x86/64bit/entry64.inc>
.text
.code32
.section ".text.long_mode_call_3arg", "ax", @progbits
@ -19,7 +21,7 @@ long_mode_call_3arg:
mov %esp, %ebp
/* Enter long mode, preserves ebx */
#include <cpu/x86/64bit/entry64.inc>
setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
/* Align stack */
movabs $0xfffffffffffffff0, %rax

4
src/cpu/x86/sipi_vector.S
View file

@ -6,6 +6,7 @@
#include <arch/ram_segs.h>
#define __RAMSTAGE__
#include <cpu/x86/64bit/entry64.inc>
/* The SIPI vector is responsible for initializing the APs in the system. It
* loads microcode, sets up MSRs, and enables caching before calling into
@ -223,7 +224,8 @@ load_msr:
#if ENV_X86_64
/* entry64.inc preserves ebx, esi, edi, ebp */
#include <cpu/x86/64bit/entry64.inc>
setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
movabs c_handler, %eax
call *%rax
#else

3
src/cpu/x86/smm/smm_stub.S
View file

@ -12,6 +12,7 @@
#include <cpu/x86/cr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic_def.h>
#include <cpu/x86/64bit/entry64.inc>
.code32
.section ".module_parameters", "aw", @progbits
@ -195,7 +196,7 @@ align_stack:
#if ENV_X86_64
mov %ecx, %edi
/* entry64.inc preserves ebx, esi, edi, ebp */
#include <cpu/x86/64bit/entry64.inc>
setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
mov %edi, %ecx

3
src/soc/amd/common/block/cpu/noncar/pre_c.S
View file

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/post_codes.h>
#include <cpu/x86/64bit/entry64.inc>
#include <cpu/x86/post_code.h>
.section .init, "ax", @progbits
@ -27,7 +28,7 @@ bootblock_pre_c_entry:
post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY)
#if ENV_X86_64
#include <cpu/x86/64bit/entry64.inc>
setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
#endif
/* Clear .bss section */

4
src/soc/intel/common/block/cpu/car/cache_as_ram.S
View file

@ -9,6 +9,7 @@
#include <cpu/x86/post_code.h>
#include <intelblocks/msr.h>
#include <intelblocks/post_codes.h>
#include <cpu/x86/64bit/entry64.inc>
.section .init, "ax", @progbits
@ -279,7 +280,8 @@ car_init_done:
andl $0xfffffff0, %esp
#if ENV_X86_64
#include <cpu/x86/64bit/entry64.inc>
setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
movd %mm2, %rdi
shlq $32, %rdi
movd %mm1, %rsi