For an unknown reason, the I2C ACPI devices were placed
under \SB intead of \SB.PCI0, as with all other non-Atom
based Intel platforms. While Linux is tolerant of this,
Windows is not. Correct by moving I2C ACPI devices where
they belong.
Also, adjust I2C devices at board level for google/rambi
as to not break compilation.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3afebbfaf56aa8cc9756d8878f9dda458d81f679
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e34a7705e6
Original-Change-Id: I4ef978214aa36078dc04ee1c73b3e2b4bb22f692
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20056
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/531720
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The supported "G41C-GS" with a nuvoton nct6776 superio is actually
G41C-GS R2.0, which is different with the more easily-found revision
G41C-GS (R1.0) with Winbond W83627DHG superio, and should be ported
separately.
Photos for the two revision:
R1.0: https://web.archive.org/web/20160915160553/http://www.asrock.com/mb/photo/G41C-GS(L1).jpg
R2.0: https://web.archive.org/web/20160717203810/http://www.asrock.com/mb/photo/G41C-GS%20R2.0(L2).jpg
BUG=none
BRANCH=none
TEST=none
Change-Id: If8236eacdc35b3b22d813265e678f0321878bfee
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1517bab693
Original-Change-Id: If60a694bcf0652ab32c0ac75ceec7e27e11fe9eb
Original-Signed-off-by: Bill XIE <persmule@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19980
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/531710
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Update devicetree PCI config based on board spec:
- enable PCIe Root Ports 5 and 9 (wifi and nvme respectively)
- enable PCIe CLKREQ on RP9, disable on RP5
- enable USB OTG
- enable P2SB
Note: PCIe RP5 is on 0.1c.0 despite this being labeled as RP1
BUG=none
BRANCH=none
TEST=none
Change-Id: I8883f75cc65b56dc22e38ec5513149c0d9205137
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: debb785d59
Original-Change-Id: Ia71ed25bd41668df1ee3e4b4e28f54482722452c
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19939
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531693
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Needed for UEFI booting via Tianocore;
with PM timer disabled, payload hangs.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0ac172b90f496e44b117e3ec9a3809d7708b85b6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0ff3b73990
Original-Change-Id: I6c65cb9d3e6a10baea4cc1e2d9e94c36fe419561
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19938
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531692
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I34e5babc9b6f059d73d02348ad0fbcff07563527
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9d8cd507a6
Original-Change-Id: Ib63e5e8a1bcbc25c288dec7d1ef6c06239ada34b
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19937
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531691
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The FSP Temp RAM init will fail if the mircocode values are set
to 0. A valid microcode update needs to be included and its size
and offset need to be set in the config.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iac912e7350662a9e56aae6eb80b70fca5c032fd3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6b8570d864
Original-Change-Id: I26d05bd7b37c8d91bf34f399c7c4189f9d3dd34a
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19936
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531690
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Adding code to setup the spd information from sodimm.
Adapted from intel/kblrvp.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iffd47fc71def3533fb7545abe753fd09df77e184
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0e977fca9c
Original-Change-Id: I0403f999dac1bdef0e9e1abe7c9c62407e223bb1
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19935
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531689
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The GPIO configuration matches the one from the original BIOS.
Some configs don't make much sense, but I kept it as is so it
would match (such as a NC pin with TX set to 1, or RXINV enabled).
Remove unnecessary early GPIO config.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id7d3d5537260431af116b017ad5860d95adf781c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 34a30a648f
Original-Change-Id: Iaec8630cef9a523fb2e2503143aa4aa72fbedc1f
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19934
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531688
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Like other devices using ENE embedded controllers, the librem13v2
requires this config option for the PS2 keyboard and mouse
(trackpad) to function properly.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6a4309052ac05fafe88e7ec61e52dcdb5a320559
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2766ebf585
Original-Change-Id: Ifba13b93a1fe2e76b2790d1c273fd9e2b5368ab0
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19933
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531687
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add the initial directory for the port of the Librem 13 v2.
The base implementation was copied from the google/chell directory
and the chell references were replaced. spd directory was removed
since the RAM is not soldered on the MB. The Kconfig, board_info.txt
and devicetree.cb files were modified to match the Librem 13 v2
hardware information. The romstage.c, mainboard.c, Makefile.in and
dsdt.asl were modified to remove chromeos specific code. The boardid.c,
chromeos.c, chromeos.fmd, cmos.layout, ec.c, ec.h and smihandler.c
files were removed from the tree, and the acpi directory was replaced
with the acpi directory from the purism/librem13 board.
These changes allow us to remove the references to chromeos specific
code and allow coreboot to compile when the librem13v2 board is selected.
BUG=none
BRANCH=none
TEST=none
Change-Id: I44e7be967bf4e72e086aa26d332ac6dd16ae0608
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 047475cbd7
Original-Change-Id: I24263fde18fcea70163dbdc59df6ea1d98c97af8
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19932
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531686
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The FADT revision was set to 5, but we do not implement the
ACPI v5.0 specification, which prevents Windows from booting.
Setting it to v3 (matching most other boards) fixes the issue
and Windows now boots normally.
Bug found by Matt DeVillier, fix tested by Youness Alaoui on
Librem 13 v1 hardware.
Please also see commits 00d250e228 (intel/skylake: Switch FADT
to ACPI version 3.0) [1] and 27e6042bb7 (intel/apollolake:
Switch FADT to ACPI version 3.0) [2].
[1] https://review.coreboot.org/19453
[2] https://review.coreboot.org/19146
BUG=none
BRANCH=none
TEST=none
Change-Id: I24a5d1d75ef0fca5b273d8d32d20812089850812
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ab5b4c19c3
Original-Change-Id: Ide97cbf64f7b05018433436431ab4723b217fe22
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19985
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/531685
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
A simple rename of the directory and the config values
and string in Kconfig/Kconfig.name/board_info.txt
It will be less confusing for users since the first models
are referred to as 'v1' everywhere now.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7a5bc84a564a6e75f0be9b34957ec09031fd368c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 3c0d7d21ef
Original-Change-Id: I23fa977717230c2001868741bb684e9633a2c0bb
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19931
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/531201
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
For an unknown reason, the I2C ACPI devices were placed
under \SB intead of \SB.PCI0, as with all other non-Atom
based Intel platforms. While Linux is tolerant of this,
Windows is not. Correct by moving I2C ACPI devices where
they belong.
Also, adjust I2C devices at board level for intel/strago
and google/cyan as to not break compilation.
BUG=none
BRANCH=none
TEST=none
Change-Id: I39d845ba3b6d07d8bb5f63f663316750f03f20a6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6a67ffb6ea
Original-Change-Id: Iaf8211bd86d6261ee8c4d9c4262338f7fe19ef43
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20055
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531193
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibca733ea7c557899ff2f8d86362cccd7a41bbcca
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 397c7b3411
Original-Change-Id: Ie0b64eadc634049f6b65cf555407337fb7c4363c
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19976
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531192
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Switch from lapic to tsc.
Allows timestamps to be used in coreboot, as there's a reference
clock available to calculate correct time units.
Clean Kconfig, remove duplicated lapic code and include tsc dir for
LGA1155 boards.
Tested on Lenovo T430.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4c179884707380e1417a251db8f70d0a915572af
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b9959e279c
Original-Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/20044
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531190
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Update user facing camera i2c address to 0x36.
BUG=None
TEST=Build & boot on soraka. Make sure user facing camera is detected.
Change-Id: Id441041035e8a2962c859cac93d02858fc84d625
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5e10422df2
Original-Change-Id: I4645ae5734faef4b6a821c04ab817a7b99da6e4b
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20023
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/531188
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add support for ELAN 5515 device.
BUG=b:62331218
Change-Id: I1be493f7fbce0a31fefdc589c063d1561a384c5e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5677e7da4b
Original-Change-Id: Id91a41743330c9e356293cfda7b2e3743dcd480c
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20040
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528264
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
BUG=none
BRANCH=none
TEST=none
Change-Id: I280a7abeada01b4d158b2d65c3b59f1b98b81ad9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e18e6427d0
Original-Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/20029
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/528259
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The coreboot sites support HTTPS, and requests over HTTP with SSL are
also redirected. So use the more secure URLs, which also saves a
request most of the times, as nothing needs to be redirected.
Run the command below to replace all occurences.
```
$ git grep -l -E 'http://(www.|review.|)coreboot.org'
| xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g'
```
BUG=none
BRANCH=none
TEST=none
Change-Id: I881e55138a6114c67585ce37d4d719fe2626b83a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a8843dee58
Original-Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/20034
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/528256
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Wrapping the long line tries to address a warning by `checkpatch.pl`,
but the line is still over 80 characters long.
BUG=none
BRANCH=none
TEST=none
Change-Id: If63c7ff3fb041b070dc815ffe05592edbb03dbec
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 619e83045a
Original-Change-Id: Ib75d4da1880624eb83f7a419cb6762f1c4c2a7b2
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/20033
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528255
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The comma-separated PCI vendor and device ID is used to associate the
VGA BIOS to the video device by using it as the file name of the VGA
Option ROM.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ideb80c381f491925dba2931448fe125a3f54e8f7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e213bf3767
Original-Change-Id: I755554eeb9a560d034d6e8fe49de619d800ea045
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/18741
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528254
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Changes the offsets of some options so that options that span multiple
bytes are byte aligned.
To make the cmos.layout file more consistent some things where moved
around in the cmos.layout of thinkpads X200 and T400.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8736136043c526817fc12f52d37a5a1db4fb95b9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 00b9f4c4b1
Original-Change-Id: Ic84a2a5dc6f9c102f041085871c2ed55e2f3692a
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18321
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/528188
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
A new variant copied from reef.
Allow override of the SKU.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia5ad68505988d7c79d64b8654b3810669a4e7940
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b09933a2eb
Original-Change-Id: Ibe160e75aa23623812f0fb9121d1d8226afc00d8
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://review.coreboot.org/20020
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/524606
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each rambi variant has a different USB port config.
Port data currently available for only candy and squawks;
other variants to be added once data obtained.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia5db0b81369ab60dbef8e59bfddd846bbd494950
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 74e1fb0b1a
Original-Change-Id: If7ce3d135d6ffe53ab1566d5258d01b052ac47f4
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19974
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/524597
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each jecht variant has a different USB port config.
BUG=none
BRANCH=none
TEST=none
Change-Id: I10e318e7bb6ea6ee3f4b0d5c210c4c7d639adce4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f069edb975
Original-Change-Id: I3b15aac9c4971e2ae230106016fba3a583ec6c9a
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19971
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/524596
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each auron variant has a different USB port config.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic677f49c4355da471c50b55afc2a6351d8e0f27d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3c3c7a1dcb
Original-Change-Id: Id17f21c23540d2e3d5a902a2174b66c7a5a5f3e0
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19970
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/524595
Since dual-channel setups use same RAM/SPD for both channels,
populate spd_data[1] with same SPD data as spd_data[0],
allowing info for both channels to propogate into the
SBMIOS tables.
Clean up calculations using SPD length to avoid repetition.
Changes modeled after google/auron variants.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4f74548fd00577e1730c4535b8ea5c59b096f3ec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cadd7c7ed3
Original-Change-Id: I7e14b35642a3fbaecaeb7d1d33b5a7c1405bac45
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19981
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/523980
sata_devslp_disable was set to work around some buggy SSD
firmware, but as it's disabled by default in both Linux and
Windows, no reason to disable at the firmware level when
many properly-functioning SSDs can take advantage of power
savings.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0f317e963dbc88a766be5da9e2266e328c4ed1ee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1a5c6201da
Original-Change-Id: Ib15f8b51db19b3d9d2e135f85c71a15a45a2ffbd
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19957
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523977
Fix for all Sandy-Bridge and Ivy-Bridge devices.
Remove unused option "hyper_threading".
Increase CMOS checksum range to cover all user adjustable settings.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3d0eab9eb780aff5e132a96fe436cae212426c69
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3de6d38642
Original-Change-Id: I02f7af13d9c82d7f531d4b49b3bc0e5a20c14b55
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19955
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/523976
This is to align with the SD_CD GpioInt setting in acpi
BUG=b:62067569
TEST=checked unused interrupt on SD_CD does not happen after s3 resume
Change-Id: Id2c151cb8549e0c447c4a1494556f1cf6a55d0ac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8cb70914ca
Original-Change-Id: I40aefcb0f571e7f6773a6d20226f357707aa041a
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20001
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523975
The separate directory was the old way of handling variant boards.
Update bakersport_fsp to the new method. All of the other pieces
were already moved into bayleybay_fsp.
BUG=none
BRANCH=none
TEST=none
Change-Id: I43f64bde643de00db0eb4c0d165651732d33b333
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 41807626e2
Original-Change-Id: I5712c1b399570bd7ab7fc9e42af25fbf15a0ba78
Original-Signed-off-by: Martin Roth <gaumless@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19077
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/523971
Light sensor isn't used and ACPI already removed, so disable
I2C5 bus interface as well.
Disable I2C6 for devices without a touchscreen
BUG=none
BRANCH=none
TEST=none
Change-Id: I82dd1cfe7fc9f5635391431dd00b7bd67b8b916a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f848ed091e
Original-Change-Id: Ib0e041ae9131615ef1140bad064de5aae91f8ee4
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19956
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523968
Remove MONOTONIC_TIMER_MSR selection from mainboard
Konfigs, as it only does a reduntant selection of
HAVE_MONOTONIC_TIMER config, already selected under
skylake soc Kconfig.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iaeecb8b10205ed68cad6890e42e6a5f1acf3c1b1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 051d6085e4
Original-Change-Id: Ib3177ceb9e8b6c16ce0e437a4a02b94f215af58f
Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20002
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/523964
Update camera sensor detail to OV 13858
Also update i2c address of OV5670
BUG=None
TEST= Build & boot to ChromeOS. Check for both the camera detection.
Change-Id: Ia097ac7da4c6dd0ceb30e930e1bd7c76cb155adc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: e7cb29493d
Original-Change-Id: I3b6192815201f605d3ebdb4bf54db26a8e837b35
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20021
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523582
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This board is almost identical to D510MO, the only differences are
some differences in populated connections, CPU with less L2 cache and
a 10/100 Realtek NIC.
The vendor uses the very same binary for both D510M0 and D410PT.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie5dab03be5bf216297431ef539248087b8a8bd2c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 80d55b3ef3
Original-Change-Id: I220515365b69e785ef249c4e3a9af5f7fddf02f9
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20000
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/522712
BUG=b:62147763
Change-Id: I87e629a15de2f6882c1bf6f238931751db7515fd
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 3178bdc345
Original-Change-Id: Iba88fed972b847448e01fcfca8c7129d950244c2
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19953
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/521040
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each slippy variant has slightly different USB port config;
data for falco and leon to be added once available
BUG=none
BRANCH=none
TEST=none
Change-Id: I0bde090fa65671806c58e5ee23d605cdc689a28a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 39480c7204
Original-Change-Id: Icc3b5b1161f62ac0b840380679acafeff363cf45
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19967
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/521039
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
All beltino variants use the exact same USB port layout.
BUG=none
BRANCH=none
TEST=none
Change-Id: I603fe9cacddb841592886724b260868323c95bb7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1186915c1f
Original-Change-Id: If5b540949ea071f7165876e12ac1ef50e62d2b22
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19966
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/521038
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Move inclusion of mainboard.asl after southbridge asl files
so scopes referenced in usb.asl are valid.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9dac338bae16f7e8ef4b68561ab60009905712a0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c5bd8b359b
Original-Change-Id: I58ea0b43f7f2c2692630df3bdb06af92566c1202
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19963
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/521035
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Port 0 is connected to SD-card reader.
Don't mark it as hot-plugable.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3f7e4bd05d2619564408514a873d847e44cef5c0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a703393612
Original-Change-Id: I5d3d4c7541683a6c09aac47ca251a6dad23ad1ab
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19928
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/521033
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
To unify the hwinfo handling along all Siemens MC boards the hwinfo
files have to be removed from the mainboard directory. They will be added
to cbfs in site-local/Makefile.inc.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9cad8d637947c76327ffe1b22152e4d524f02424
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7a3d6e1435
Original-Change-Id: Ia3dcb2e0118527b37aed872740273c4fa7004aef
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19982
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/521032
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The prior used RTC PCF8523 is replaced with RX6110SA on this mainboard.
Switch to the new RTC in Kconfig and adapt devicetree to the new chip.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6aedee70a912bce4c5c1c651aa8d4c4363b0f632
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: cd37fef2e1
Original-Change-Id: I7c4911191cae254900f9a958da42ecd18497484c
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19979
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/521031
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Modify the DPTF configuration on Eve to relax the severe throttling that
is currently applied and allow performance testing to see better results.
BUG=b:35581264
TEST=performance tests show better results and thermal tests still pass.
Change-Id: I3b2c10e68c6772453fbc16094e9d00d950d872b7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 07a597feff
Original-Change-Id: I0838f4ec3026bc8bac814698043fa97cf6772cb4
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19947
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/521029
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Instead of having the SMI handler power off the touchscreen on the
way into suspend add power resource controls to the ACPI device so
the power is managed by the kernel instead of the BIOS.
BUG=b:35581264
TEST=manual testing on Eve to ensure that the touchscreen is still
functional at boot and after suspend/resume, and that it does not
draw power in suspend.
Change-Id: Ic1dd4ed8faab367347a4150c415a5cd40adb25f6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f124b88cfb
Original-Change-Id: Id9a98807d24bbc7dff32408f3d113f6fad5bc023
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19946
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/521028
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The Tegra210 SoC never had a proper cpu_reset() implementation, so it's
pointless to pretend there is one. Most ARM SoCs/boards only define
hard_reset() at the moment anyway, so let's stick with that.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifeb6b0b2a4417bdb13908ceb0aa4e382b40a91c5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c25b2a18fa
Original-Change-Id: I40f39921fa99d6dfabf818e7abe7a5732341cf4f
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19786
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/521025
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Get rid of mainboard_io_trap_handler.
The only purpose is to enable tp-smapi, but is already done on all
boards in h8_enable, as of devicetree setting config0.
BUG=none
BRANCH=none
TEST=none
Change-Id: If248d0142568db0f89b18225335bd8f336c55570
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 8953d4a137
Original-Change-Id: I33fd829a7e34aefa8f76ca6020cc8e802f7aab17
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19790
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/517937
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Instead of assuming the mapping of dimm number to SPD SMBus address,
allow the mainboard to provide its own mapping. That way, global
resources of empty SPD contents aren't wasted in order to address
a dimm on a mainboard that doesn't meet the current assumption.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1ef87d18b30192be730805238df62ff81f130339
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dd82edc388
Original-Change-Id: Id0e79231dc2303373badaae003038a1ac06a5635
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19915
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/517936
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
GPP_C2 is being used as strapping option, so
should not be set to NF. Signal was floating
previously, which can lead to an assertion of
smbalert#.
BUG=b:37681121, b:35775024
BRANCH=None
TEST=powerd_dbus_suspend and ensure stays in suspend
Change-Id: Ife5a3d8c442e3f29c2dc549b9f6887d526cbf8f2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c96f757af1
Original-Change-Id: I68091206014621419b886b723a5681541be989bc
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19904
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/517935
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
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