This reverts commit aa6865291a.
Reason for revert: We applied this patch for touchpad stuttering issue
for XOl, but the same touchpad problem was reported. So we would revert
this change and apply kernel patch (crrev/c/5808335) to avoid the
touchpad issue.
Change-Id: I78139932e76dbd4128fb325dd70b7dcff3bcc81c
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add get_wifi_sar_cbfs_filename(). This function uses the FW_CONFIG
for WIFI_CATEGORY to choose the right wifi_sar hex file.
Below is the file mapping:
wifi_sar_0.hex = wifi6
wifi_sar_1.hex = wifi7
BUG=b:345596420
TEST=emerge-nissa coreboot chromeos-bootimage
Cq-Depend: chrome-internal:7607427
Change-Id: If8339a2a1d32d3e885ef87ea2ec2847f107f1fbd
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84051
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Iccmax of VccIn_Aux is 25A with MBVR design.
BUG=b:348258637
TEST=Local build successfully and boot to OS normally.
Change-Id: I59c420c03a8f01d185f616a2212798266b4251e0
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
EE change GPP_C1 from pull-up to OD&no pull-up in PCH GPIO Table.
BUG=b:358472598
TEST=Build and verified test result by EE team
Change-Id: I84d1b42a39bebbcd610cebc46f979018fc79238f
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83904
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PCIE WLAN Bluetooth is on port8, need to correct USB port for PCIE WLAN
bluetooth companion device.
BUG=b:345596420
TEST=Build and test on nivviks, check BRDS is shown in SSDT.
Change-Id: I0908ff500434401bf89a5313427cf304f32cf929
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
PCIE WLAN Bluetooth is on port8, need to correct USB port for PCIE WLAN
bluetooth companion device.
BUG=b:345596420
TEST=Build and test on revin, check BRDS is shown in SSDT.
Change-Id: Ie8174567b863e1afe8b0a27e644e24e9d3de6d19
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84020
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Add the condition of unprovisioned fw_config to enable all storages
and devices. It's for first boot on all storags and preliminary test
in factory when fw_config is unprovisioned.
BUG=None
TEST=Build jubilant firmware and boot to OS on storages when fw_config
is unprovisioned and ensure all devices are enable.
Change-Id: Ia14632744c34548e2c201dfc58d82515cdd02df0
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84002
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Storage devices are very critical to boot to OS. When probe list is
defined for storage devices, all of them get disabled when fw_config is
unprovisioned - a typical situation in the factory. Fix this by
configuring the storage devices in device/override tree to probe and
enable them when fw_config is unprovisioned.
BUG=None
TEST=Build Brox firmware and boot to OS when fw_config is unprovisioned.
Change-Id: I0537f7d1d83293b9b3408f0aadf11fa2e7908163
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83984
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the voltage value measured by the USB2 pin of the wlan is 500mv,
it does not meet the design requirements. Adjusting the port length
can reduce the voltage to 450mv, which meets the expected settings.
BUG=b:361037189
TEST=1. The voltage measurements are as expected.
2. The Bluetooth and WiFi functions of the wlan module are
verified to be normal.
Change-Id: Icd1ec3b561ee5b3f55e5f97a56fd9cb7df893508
Signed-off-by: zengqinghong <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Enables early serial console for debugging.
TEST=build/boot drobit, verify console output available starting in
bootblock on CPU UART (/dev/ttyUSB1) vs ramstage.
Change-Id: If94eb8caca3469143433fef06b972050f886be6a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This mainboard does not have AT24RF08C (Asset Identification EEPROM) and
will show "*INVALID*" in the SMBIOS table.
Change-Id: If6f948bc4c63c7afdc8b31e1945d3c3beb99883f
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Enable Intel CrashLog diagnostic feature by default on all Google
Dedede variants.
BUG=b:354834461
TEST=Built for Google Dedede and verifed that CrashLog is enabled by
default.
Change-Id: Ib0487bd6a5bfdad2a80fd0787e009e48f4527d38
Signed-off-by: Jędrzej Ciupis <jciupis@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Kinox has two VBT options, selected via fw_config. Add the second
option to CBFS, and update the original file.
Extracted from Google_Kinox.14505.704.0.bin.
TEST=build/boot kinix, verify firmware display init successful and
payload menu visible. Verify correct VBT selected via cbmem log.
Change-Id: I01c19222628fee3874ef592ec40b40d9bd679dce
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83996
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The power off code in depthcharge disables all GPEs prior to power off.
The problem is that for gpio wake sources that are locked, this power
off code cannot successfully clear any pending interrupt from that
source. This can result in the device incorrectly waking back up after
it's been powered off from the firmware dev screen.
BUG=b:360380950, b:359692570
BRANCH=None
TEST=verify brox DUT is able to power down and stay powered down when
selecting the "Power off" button in the firmware dev screen.
Change-Id: I5cd36640677996209beb8fe29f522ff8e07ebf00
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
The power off code in depthcharge disables all GPEs prior to power off.
The problem is that for gpio wake sources that are locked, this power
off code cannot successfully clear any pending interrupt from that
source. This can result in the device incorrectly waking back up after
it's been powered off from the firmware dev screen.
BUG=b:360380950, b:359692570
BRANCH=None
TEST=verify rex DUT is able to power down and stay powered down when
selecting the "Power off" button in the firmware dev screen.
Change-Id: I3fdc02a82d197fd2b075e0a66c578149cef3a69f
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
The power off code in depthcharge disables all GPEs prior to power off.
The problem is that for gpio wake sources that are locked, this power
off code cannot successfully clear any pending interrupt from that
source. This can result in the device incorrectly waking back up after
it's been powered off from the firmware dev screen.
BUG=b:360380950, b:359692570
BRANCH=firmware-brya-14505.B
TEST=verify brask, nissa, or brya DUT is able to power down and stay
powered down when selecting the "Power off" button in the firmware dev
screen.
Change-Id: Ic0ac73f8f29761f072d42f35e97198b56d32a9bc
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
With commit 26b1a5f62b ("mb/acer/g43t-am3: Rework mainboard for variant
mechanism"), the files related to the G43T-AM3 mainboard were supposed
to be moved into its own variant directory. However, it seems it was
forgotten to delete the old ones and thus remove the duplicates.
Change-Id: I450fab074621d21e80216e4667eaf2510b0e14ad
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83985
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the ITE mirror functionality; all devices will mirror
automatically when they exit G3, and this is good enough.
Change-Id: I9b82e1b1386b4607dfe7da9b25ba432ec0303cf8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83629
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previously RAM probing was necessary for our QEMU-RISCV target in order
to find the available amount of memory.
Now we get the memory from the devicetree propagated by QEMU, so there
is no reason to keep it anymore.
Tested:
Start QEMU-RISCV and cause an exception to make sure the trap handler
still works.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9b1e0dc78fc2a66d6085fe99a71245ff46f8e63c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83873
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust settings as recommended by thermal team.
Set tcc_offset value to 12 in devicetree.
BUG=b:308704811
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot chromeos-bootimage
built bootleg and verified test result by thermal team
Change-Id: I0ae97bb0b2dbb2fe8f35221522506ec1f7da47f6
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83971
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
BUG=b:345596420
TEST=Build and test on revin, check BRDS is shown in SSDT.
Change-Id: I87cfbdd0b8a97d84a96af373855219c60f39f173
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
BUG=b:345596420
TEST=Build and test on nivviks, check BRDS is shown in SSDT.
Change-Id: Ib654f22033c68edbc602f14537aaa2151800598d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83943
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change STORAGE_UNPROVISIONED to STORAGE_UNKNOWN depend on depthcharge setting.
BUG=None
TEST=emerge-brox coreboot
Set STORAGE_UNKNOWN on jubilant, check that NVMe and UFS can boot.
Change-Id: I4cfd7322c2940862dfbae46e85522715cd7534c1
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83935
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
This patch removes WWAN configuration from the bootblock.
It appears that setting it up in the bootblock may not be necessary.
Configure in bootblock,the seq will be triggered at the same time.
The customer would like us to leave some buffer for EN to RST.
BUG=b:357764679
TEST=Build and verified test result by EE team
Change-Id: I2c0e789c0bec293f4bca711e53644d62f4f83551
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83792
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds a new board as a variant of the Acer G43T-AM3 with the
following prominent changes:
* Intel Q45 northbridge (GMCH) instead of a G43
* 4 MiB of flash instead of 2 MiB
* Two serial ports (one external, one internal)
* A parallel port connector (internal)
* An FDD connector
* DVI-D instead of HDMI
* No Firewire
The port was done based on logs and info received via private email. It
was only tested on the Acer G43T-AM3 so far, which still builds and works.
Change-Id: Ic2654ca4b198bfea409992be14e89702cf67ea50
Signed-off-by: Julia Kittlinger <launchpad.vineyard395@passinbox.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
In preparation for CB:83968, rework the configuration files and move
files specific to G43T-AM3 to its own variant directory.
Change-Id: I425852f4bdacf7cb6688a5fb845ac3001373262e
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Signed-off-by: Julia Kittlinger <launchpad.vineyard395@passinbox.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57764
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch calls `xhci_host_reset()` function to perform XHCI
controller reset.
Currently, the PMC IPC times out while sending the USB-C (0xA7) command
during poweron from S5 (S5->S4->S3->S0).
On Brya variants, poweron from S5 state results in PMC error while
sending PMC IPC (0xA7) to USB-C active ports, log here:
localhost ~ # cbmem -c | grep ERROR
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0x200a7 failed
[ERROR] pmc_send_ipc_cmd failed
[ERROR] Failed to setup port:0 to initial state
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0x200a7 failed
[ERROR] pmc_send_ipc_cmd failed
[ERROR] Failed to setup port:1 to initial state
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0x20a0 failed
This problem is not seen while powering on from G3 (G3->S5->S4->S3->S0).
During poweron the state of USB ports are not the same between S5 and G3
and it appears that the active USB port still is in U3 (suspend) while
PMC tries to send the IPC command, which results in a timeout.
This patch utilises the S5 SMI handler to reset the XHCI controller
using `xhci_host_reset()` prior entering into the S5, it helps to
restore the port state to active hence, no PMC timeout is seen with
this code change.
Supporting Doc=Intel expected to release a TA (Technical Advisory)
document to acknowledge this observation and supported W/A for ADL
generation platforms.
Till that time, keeping this W/A as part of the google/brya specific
mainboard alone.
Note: other ADL-SoC based mainboards might need to apply the similar
W/A.
BUG=b:227289581
TEST=No PMC timeout is observed while sending USB-C PMC command (0xA7)
during resume from S5.
Total Time: 1,045,855
localhost ~ # cbmem -c | grep ERROR
No PMC timeout error is observed with this CL.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibf06a64f055a0cee3659b410652082f31e18e149
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Recently merged commit 8cc1d79ed0 (mainboard/qemu-aarch64: Get top
of memory from device-tree blob) missed a rebase and hence needs the
include path updated.
Tested `make qemu` for qemu-aarch64.
Change-Id: Id669eeaabbc1710bb7e408659f2d79f682427919
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Trying to probe RAM space to figure out top of memory causes an
exception on AArch64 virtual machines with recent versions of QEMU, but
we temporarily enable exception handlers for that and use it to help
detect if a RAM address is usable or not. However, QEMU docs recommend
reading device information from the device-tree blob it provides us at
the start of RAM.
A previous commit adds a library function to parse device-tree blob that
QEMU provides us. Use it to determine top of memory in AArch64 QEMU
virtual machines, but still fall back to the RAM probing approach as a
last-ditch effort.
Change-Id: I4cc888b57cf98e0797ce7f9ddfa2eb34d14cd9c1
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80364
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
1.Set unused device's GPIOs to NC based on fw_config.
2.Disable config for nvme, ufs and CNVi based on fw_config.
3.Add fw_config STORAGE_UNKNOWN to enable all storages
for the first boot in factory.
BUG=None
TEST=emerge-brox coreboot chromeos-bootiamge
check fw_config messages in ap log
verify devices on/off by fw_config on jubilant
Change-Id: I8d9f4edea454e0861f91261bf13fa80572d0a181
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Locking GPP_F15 causes DUTs with fingerprint sensor to not be able to
correctly power down and stay powered down. This pin does not need to
be locked.
BUG=b:359692570, b:356750516
BRANCH=firmware-brya-14505.B
TEST=`FW_NAME=gimble emerge-brya coreboot chromeos-bootimage`, flash and
boot gimble into developer mode, then reboot into dev screen and select
the "Power off" button and verify gimble powers off and does not power
itself back up.
Change-Id: I1c73035b02021b0d1268cd46dcd0841621556ad5
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83932
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The AP console log contains "HECI: No CSE device" and the system cannot be entered.
BUG=b:359474142
TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki
The "HECI: No CSE device" message for AP log disappered
Change-Id: I488056dc8bca2174dd96c28793e3202b7aae890c
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83905
Reviewed-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This reverts commit 2eb5c1e83e.
Reason for revert: The latest release of FSP will not boot
without a display being connected using this VBT. The original
VBT does not have this issue, nor is the original issue that
commit 2eb5c1e83e fixed.
Revert it to restore booting when there is no display.
Change-Id: I05f9037cd68b8b29e69156e2372a544985f4442e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
In next phase, riven will remove external fivr. Use the board version
to config external fivr for backward compatibility and show message.
BUG=b:359062365
TEST=build, boot to OS, suspend/resume work normally.
Change-Id: Id5f538b2eda7820a922b8d9ee14b2bae7df3726c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Brox does not have PCIe WWAN or discrete GPU. Hence no need to power
them off during suspend. Hence also remove the MPTS ACPI method.
BUG=None
TEST=Build Brox firmware and boot to OS.
Change-Id: Ia239c3f038ce31934efb0a391350fa0f786e3fcd
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83788
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables the TCSS XHCI in the devicetree to solve the genesys
hub enumeration issue.
BUG=b:348332200
TEST=Able to build google/nova and ensure lsusb can list genesys
hub device.
Change-Id: Ic8e25756a2975e884434c4c7e3d587f4c1f0ed0b
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83845
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Confirm with EE, the GPP_C1 don't need PU 20K.
So modify GPP_C1 setting to remove PU 20k
Schematic version: 500E_GEN4S_ADL_N_MB_0418
BUG=b:358162951
TEST=Build and boot on pujjoga.
Change-Id: I7ad16cd29ab467d3eac74dab40522c577d91c747
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83818
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
1. The P sensor need follow WWAN FW_CONFIG to enable/disable
2. Modify GPP_H19 setting to PAD_CFG_GPI_APIC to fix PLT test fail
Schematic version: 500E_GEN4S_ADL_N_MB_0418
BUG=b:357998089
TEST=1. Boot to OS and verify the P sensor devices is set based on
fw_config.
2. Confirm that the PLT test can pass successfully.
Change-Id: Ic3610180c8cf99eba9367e26bfc3666410af19f7
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This change adds the necessary configuration for the elan
touchscreen (ELAN9004) device, connected to I2C bus 16.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset, stop and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
BUG=b:348125053 b:348126380
TEST=emerge-nissa coreboot
boot with elan TS, make sure elan TS is functional.
Change-Id: I64c5a11dfaacfcca34240375d4dca5c76a60f62e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83876
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
