Commit graph

4 commits

Author SHA1 Message Date
Jincheng Li
179b8444c3 soc/intel/xeon-sp/gnr: Hook up public FSP bin and headers
GNR-AP public FSP
- https://github.com/intel/FSP/tree/master/BirchStreamFspBinPkg/ap

GNR-SP public FSP
- https://github.com/intel/FSP/tree/master/BirchStreamFspBinPkg/sp

GNR mainboards will by default use public FSP bin and headers.
If needing to use site-local FSP bin and headers, apply below
settings in the defconfig (use beechnutcity CRB as example),

CONFIG_FSP_USE_REPO=n
CONFIG_ADD_FSP_BINARIES=y
CONFIG_FSP_T_FILE="site-local/beechnutcity/Server_T.fd"
CONFIG_FSP_M_FILE="site-local/beechnutcity/Server_M.fd"
CONFIG_FSP_S_FILE="site-local/beechnutcity/Server_S.fd"
CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/
graniterapids/sp/"

TEST=Build and boot on intel/avenuecity CRB
TEST=Build and boot on intel/beechnutcity CRB

Change-Id: I88701316e21ec4737539294d17926aa0abe8c1fd
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88898
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Hancockc <hancock.chang@mitaccomputing.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Schumi Chu
Reviewed-by: Wilson-MiTACComputing <wilson.chien@mitaccomputing.com>
Reviewed-by: Mark Chang <mark.chang@mitaccomputing.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-08-27 17:13:33 +00:00
Jincheng Li
3828153ea5 soc/intel/xeon_sp/gnr: Use official microcodes
Use microcode updates from intel-microcode submodule by default.
Downstream users can still decide to use their own files.

TEST=Build and boot on intel/avenuecity CRB
TEST=Build and boot on intel/beechnutcity CRB

Change-Id: I5a37423426b19dc9ec76984df5ad9c6d2a28f83b
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2025-07-22 16:30:02 +00:00
Shuo Liu
495b705137 configs/builder: Update PBP path for Gen6 Xeon-SP boards
Gen6 Xeon-SP boards needs to be provided with platform boot policy
blob.

Change-Id: I22b944ab6bcb2b9d0797833c06410bdc523e2709
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-10-23 10:30:26 +00:00
Gang Chen
921ddba69e mb/intel/avenuecity_crb: Add GNR/SRF-AP 2S server board Avenue City
Avenue City CRB is the 2 socket reference board for 6th Gen Xeon-SP
AP SoCs (Granite Rapids AP and Sierra Forest AP).

This patch initially sets the code set up as a compilation target
with GNR N-1 FSP, and with basic feature supports (Integrated IO
Controller (IIO) configuration, BMC, UART, HPET).

TEST=Build on intel/avenuecity CRB

Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Co-authored-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-16 20:55:05 +00:00