Since we are not using gpio regulators on reef anymore, remove the
selection from Kconfig as well.
BUG=None
BRANCH=None
TEST=Compiles successfully.
Change-Id: Iaa6ef0c06a23d42c0d92a57a7b3bbf634c4d14d5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: abd5d1d35c
Original-Change-Id: Iae7d88dec3ac476d65b292f97a6ba3add71ce07a
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18399
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445139
Using x86 RDRAND instruction, two functions are supplied to
generate a 32bit or 64bit number.
One potential usage is the sealing key generation for SGX.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve to generate a 64bit random number.
Change-Id: I5e2768ba499f1e008c9b68feae68b368cedaaa39
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 18792314d7
Original-Change-Id: I50cbeda4de17ccf2fc5efc1fe04f6b1a31ec268c
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18362
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445138
Currently the USB OC pins definition only being defined up to OC3.
For PCH-H, OC4 and OC5 are needed, so add both into OC pin enum.
Changes is being verified and booted to Yocto with Saddle Brook.
BUG=none
BRANCH=none
TEST=none
Change-Id: I48ed19f800726d1220c0110cd3a7fdcb53b760dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f296ce91b9
Original-Change-Id: Idaed6fa7dcddb9c688966e8bc59f656aec2b26eb
Original-Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18364
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445137
Move code common code from each variant's mainboard.asl into
common ACPI code for all variants (like google/auron). This also
adds the _PRW method for the LID0 device for falco and peppy, which
omitted the function when they were originally upstreamed.
See Chromium commit c8b41f7, falco: Add _PRW for LID0 ACPI Device
BUG=none
BRANCH=none
TEST=none
Change-Id: I9199128d0270e1ed6f2600282216950a592001df
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4b8252ed76
Original-Change-Id: I7f5129340249a986f5996af37c01ccbde8d374e8
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18368
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445136
Apply the measured rise and fall times for I2C bus 1 on Eve
so it can be tuned properly for 400KHz operation.
BUG=chrome-os-partner:63020
TEST=verify I2C1 bus speed with a scope
Change-Id: I4bd676d69f77cc8c90cf3c2eb6d29776039aee15
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c86fa6d975
Original-Change-Id: I32b5aa460ea35aadca7f3d52324a64880764919f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18396
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445135
Currently UART0 GPIOs are being put into native mode during FSP-S
stage, so have ramstage re-configure them back to regular GPIO mode.
GPP_C8 does not seem to be functioning properly when routed to the
APIC, possibly due to the UART0 being enabled even though it is unused,
which is required because UART0 is PCI 1e.0 and so must be present for
other 1e.x functions to be enumerated. Instead, use this pin as a GPIO
interrupt so it will be routed through the GPIO controller at IRQ 14.
GPP_C9 was inverted and was only working because the pin was being
re-configured in FSP-S.
Also export the reset gpio as a device property so it can be used by
the kernel driver, which will stop it from complaining at boot.
BUG=chrome-os-partner:61233
TEST=verify that the interrupt and device is functional in the OS
Change-Id: Idca8e787f9d99f2bba03f103ae6fcf0d49ad6a3f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6c8238521e
Original-Change-Id: Iaf9efbf50a13a981c6a9bbd507475777837e9c12
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18395
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445134
There is an enable_s0ix config option in the devicetree that should
be used to disable it when not set:
- do not export C8/C9/C10 C-states in _CST
- do not enable SLP_S0 in FSP
BUG=chrome-os-partner:58666
TEST=test on eve board to ensure that OS only sees 3 ACPI C-states
instead of 6 and that it no longer attempts to enter C10
Change-Id: Iabec05c85df22899c04ad5eeb77923fc3e1caf26
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 25c7d9342b
Original-Change-Id: I90e4dc776d1d17d0b700cda63c8476786cd2e4ff
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18394
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445133
Add support for more ACPI features in the generic SPI ACPI
driver so it can be flexible enough to support more devices,
or devices in different configurations.
- add a wake pin
- add support for using IRQ GPIO instead of PIRQ
- add power resource support with enable and reset gpios
BUG=chrome-os-partner:61233
TEST=ensure existing SSDT generation is unchanged,
and test that new features generate expected code
Change-Id: Ib4dcba5b0d57539030eb380a9ec38db9f7aea9a7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c9db384ea4
Original-Change-Id: Ibe37cc87e488004baa2c08a369f73c86e6cd6dce
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18393
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445132
Add individual macros for the various interrupt types so
they can be used in devicetree.
BUG=chrome-os-partner:58666
TEST=nothing uses this yet, will be used in an upcoming commit
Change-Id: I191f422ec4216ecc70896a3b33ebbb62955053b4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4f31d5c2ce
Original-Change-Id: I2a569f60fcc0815835615656b09670987036b848
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18392
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445131
Move the function that adds a power resource block from
i2c/generic to the acpi device code at src/arch/x86/acpi_device.c
so it can be used by more drivers.
BUG=chrome-os-partner:61233
TEST=verify SSDT table generation is unchanged
Change-Id: I20371b7a7f4e270cd1c61a3e8b9b58b10cafc8ed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bd73dbbc38
Original-Change-Id: I0ffb61a4f46028cbe912e85c0124d9f5200b9c76
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18391
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445130
Prmrr configuration is supported by Kabylake FSP-M with UPD provided.
It is required as one of the SGX initialization steps in BIOS.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified uncore PRMRR MSRs get programmed to set
size and boot.
Change-Id: I4bf81697e1fa2a2329b67d1b228a329c3a42fc3e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e65affa2ed
Original-Change-Id: I2b3dc7c92487505165ee429bd1a37bd60ceac8f3
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18361
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445129
Created using autoport plus some manual work and copying from G505S to
account for the non-H8 EC.
This model uses the same ENE KB9012 EC as the G505S.
Tested:
- Mainboard variant with 8GB Elpida DDR3
- SeaBIOS payload
- Booting into Linux 4.9.6 with Debian/unstable installed on the
internal HDD/SDD slot
- Native raminit
- Both native VGA init and option rom VGA init
- Basic TPM functionality (auto-detection and RNG)
- Battery status readout
- Basic ACPI functions (power button event; power-off; reboot)
- thinkpad-acpi hotkey functions
- thinkpad-acpi LED control (red thinkpad LED)
- Suspend to RAM and resume works
- Mini displayport output works
Known issues:
- Patches needed for EC battery support
https://review.coreboot.org/#/c/18348/https://review.coreboot.org/#/c/18349/
- No thermal zone since temperature sensing is not H8-compatible
and needs to be reverse engineered.
Not tested:
- msata/wwan (probably works)
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifd82918d0eb93002027b9ed841e138419691c854
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cee930a39b
Original-Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Original-Change-Id: I52bc4515277e5c18afbb14a80a9ac788049f485c
Original-Reviewed-on: https://review.coreboot.org/18351
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/445636
This mainboard uses two i210 Ethernet controller. Therfore we enable the
usage of the i210 driver and have to provide a function to search for a
valid MAC address for all i210 devices by using Siemens hwilib.
BUG=none
BRANCH=none
TEST=none
Change-Id: I70c71081b5a190304a2f36c4f185c9564822f0d6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 480eab0da9
Original-Change-Id: I36246cdef987fcece15a297ebb2f41561fca1f69
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/18380
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/445155
Not selecting the Kconfig option `GENERATE_SMBIOS_TABLES` the build
fails with the error below.
```
CC ramstage/ec/lenovo/h8/h8.o
src/ec/lenovo/h8/h8.c:201:2: error: unknown field 'get_smbios_strings' specified in initializer
.get_smbios_strings = h8_smbios_strings,
^
src/ec/lenovo/h8/h8.c:201:2: error: initialization from incompatible pointer type [-Werror]
src/ec/lenovo/h8/h8.c:201:2: error: (near initialization for 'h8_dev_ops.read_resources') [-Werror]
cc1: all warnings being treated as errors
```
So add the appropriate preprocessor guards to fix the build error.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8d29e84c4664871193e0ca6e40ea22554caea1ad
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2a4a452abc
Original-Change-Id: I3baed452d422539a805c628a8c4a6a8c2a809317
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/17770
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/445154
Setting both bits 27 and 7 of PCH register PMSYNC_CFG (PMSYNC
Configuration; offset 0x33c8) causes pre-OS display init to fail
on HSW-U/Lynxpoint and BDW-U ChromeOS devices when the VBIOS/GOP
driver is run after the register is set. A re-examination of
Intel's reference code reveals that bit 7 should be set for the
LP PCH, and bit 27 for non-LP, but not both simultaneously.
The previous workaround was to disable the entire power optimizer
section via a Kconfig option, which isn't ideal.
Test: unset bit 27 of PMSYNC_CFG and boot google/lulu,
observe functional pre-OS video output
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie0cc1b294a4f8722bdd3a79faef1516f503d2e03
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c97e042a9b
Original-Change-Id: I446e169d23dd446710a1648f0a9b9599568b80aa
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18385
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445153
We've been able to narrow down the problem to a single register/
single bit, so revert this commit and address the problem in a
follow-on commit.
This reverts commit 0f2025da0f.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0e986e2be69c6e74eb57c70b13cf625b0317c44d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ee6a612eb2
Original-Change-Id: I780f9ea2976dd223aaa3e060aef6e1af8012c346
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18384
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445152
Add a test in case we have a DIMM2 not populated but DIMM3 is.
BUG=none
BRANCH=none
TEST=none
Change-Id: I80508fd652795593aef7e202891b494d60d4d6a9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 75da1fb2ba
Original-Change-Id: I14f82afe03884740570838e7b2771233356c518d
Original-Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Original-Reviewed-on: https://review.coreboot.org/18386
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/445150
Coverity is detecting 'sp' as a variable which has not been initialized.
This is obviously not correct, so this patch *TRIES* to mark it as false
I'm not positive that this will work because the annotation needs to go
on the line above the error, but this error is inside of a # define.
Does the whole #define count as one line? Can it go on the line
above the #define in the .h file? Does it have to precede every line
where the #define is used? The documentation doesn't make this clear.
Should suppress coverity issues: 1368525 & 1368527
uninit_use: Using uninitialized value sp.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8fa056af3e829218d8139f3899b7291e62ea6796
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f797a1ac6a
Original-Change-Id: Ibae5e206c4ff47991ea8a11b6b59972b24b71796
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18247
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://chromium-review.googlesource.com/445149
The hybrid driver select by DRIVERS_LENOVO_HYBRID_GRAPHICS doesn't work
for t400/t500.
Replace it with a custom romstage implementation.
Tested on Lenovo T500 with dual graphics:
* Intel Native GFX init
* AMD VBios
* GNU Linux 4.8.13
* SeaBios as payload
* Discrete is working (44 W)
* Integrated is working (24 W)
* Switchable is working (34 W)
** Both GPUs are enabled, with Intel being connected to the panel
** DRI_PRIME allows to use AMD GPU
** ACPI doesn't seem to work (no vgaswitcheroo)
Depends on Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422
Depends on Change-Id: If389016f3bb0c4c2fd0b826914997a87a9137201
BUG=none
BRANCH=none
TEST=none
Change-Id: I8319fb3c52c32b548820f49dea0aee53b8e509d3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f9d5308690
Original-Change-Id: I7496876e9b434d4a2388e1ede27ac604670339b7
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18010
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/445147
It rewrites the results of receive enable stored in the upper nvram
region, to avoid running receive enable again.
Some debug info is also printed about the self-refresh registers.
(Not enforcing a reset here, since 0 does not necessarily mean it's
not in self-refresh).
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie8a85069cc613706c1405e150bece11bc6ba43c1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ef7e98a2ac
Original-Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/17998
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445144
Previously the raminit failed on hot reset and to work around this
issue it unconditionally did a cold reset.
This has the following issues:
* it's slow;
* when the OS issues a hot reset some disk drives expect their 5V
power supply to remain on, which gets cut off by a cold reset,
causing data corruption.
To fix this some steps in raminit must be ommited on the reset path.
This includes receive enable calibration.
To achieve this it stores receive enable results in RTC nvram for them
to be rewritten on the resume path.
Note: The same thing needs to be done on the S3 resume path.
Calling a hot reset after raminit "outb(0x6, 0cf9)" works.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7abad55524ecea8bbd828aba6dd3ce7708f1a7bd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 97e13d84c3
Original-Change-Id: I6601dd90aebd071a0de7cec070487b0f9845bc30
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18009
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/445143
Maxim 98927 kernel driver requires entries in the ACPI SSDT table,
add a SSDT generator as part of this driver.
BUG=chrome-os-partner:62051
BRANCH=None
TEST=After boot, dump and verify that the generated SSDT ACPI table has the
required entries.
Change-Id: I9043f9f0b66b45d04e8b8cbe8c99b77686fd5666
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4979d7610e
Original-Change-Id: Ic2d4d8449288bc00d085852220b2e1e7a208e9ef
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Signed-off-by: M Naveen <naveen.m@intel.com>
Original-Signed-off-by: Dylan Reid <dgreid@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18211
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445127
Currently there is no distinction between mainboards using
Skylake or Kabylake SoC, Add a config option for Kabylake
SoC to allow mainboards to explicitly select if they are
using it.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1c0e5acebce9db7e06e2e320dbdf67d6c63061b7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0700dca969
Original-Change-Id: Ie7960bd81f88a223894afe3115ddc0bc637e4be4
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18312
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445124
There are MSRs that are programmable per-core not per-thread, so add
a function to check whether current executing CPU is a primary core
or a "hyperthreaded"/secondary core. For instance when trying to
program Core PRMRR MSRs(per-core) with mp_init, cpu exception is thrown
from the secondary thread. This function was used to avoid that.
Potentially this function can be put to common code or arch/x86 or cpu/x86.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified core PRMRR MSRs get programmed only on primary
thread avoiding exeception.
Change-Id: I6d837f50db404f35606f1f975b05456946605c10
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 2b194d9741
Original-Change-Id: Ic9648351fadf912164a39206788859baf3e5c173
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18366
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444818
scan_smbus routine does not perform any smbus specific operation. Thus,
rename the routine to scan_generic_bus so that it can be used by other
buses like SPI. Add a wrapper scan_smbus to allow other users of smbus
scan to continue working as before.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully
Change-Id: Id2b6342d96915e47c265c7984f651680632a3903
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 4e08479688
Original-Change-Id: I8ca1a2b7f2906d186ec39e9223ce18b8a1f27196
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18363
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/444809
Add support for a new "SPI" device type in the devicetree to bind a
device on the SPI bus. Allow device to provide chip select number for
the device as a parameter.
Add spi_bus_operations with operation dev_to_bus which allows SoCs to
define a translation method for converting "struct device" into a unique
SPI bus number.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully.
Change-Id: Id5ef64e11a862f4075afa06a7eca25bfc84fc9aa
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 7606c377f5
Original-Change-Id: I86f09516d3cddd619fef23a4659c9e4eadbcf3fa
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18340
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/444808
This commit makes a basic adjustment for GPIOs, device tree, flash map and
MRC settings. With these basic settings the mainboard boots into
Linux lubuntu 4.8.0-22-generic using SeaBIOS. More adjustments will follow.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic79be51b2d99ebbc2629e19f6110ad10f12028ab
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 6abdbcd4dc
Original-Change-Id: Ia920d236814f2e6a9b777dd1e4b4feef0ddf7721
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/18292
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/443925
The four options are only used in X86:
- BOOTBLOCK_SIMPLE
- BOOTBLOCK_NORMAL
- BOOTBLOCK_SOURCE
- SKIP_MAX_REBOOT_CNT_CLEAR
Move them all into src/arch/x86/Kconfig - this puts them in the chipset
menu instead of general setup.
Verified that this makes no significant changes to any config file.
BUG=none
BRANCH=none
TEST=none
Change-Id: If9a61ed8a0b9add3b4f70dfb15ea0213c452f584
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 408fda799a
Original-Change-Id: I2798ef67a8c6aed5afac34322be15fdf0c794059
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/17909
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/443682
For boolean types, 'n' is the default default value - it doesn't
NEED to be set. If it IS set, it prevents a later default from
being set. So by removing the 'default n' statements from the
early symbols, they can be overridden other places in the tree.
Verified that this makes no significant changes to any config file.
BUG=none
BRANCH=none
TEST=none
Change-Id: If1d6e0be8feb731f073b7b3815504e6cd1957976
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: c8d16f4933
Original-Change-Id: I1b5b66bd8a3df8154a348b5272c56c88829b3ab4
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/17908
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/443681
Some variants need the internal pull resistor on GPIO_SSUS_40
set explicitly to pull down rather than disabling the pull,
in order for the ram-id to be read correctly via GPIO.
Correct this by adding a function to enable and set the internal pull
and define its use as needed in the board's variant.h.
Chromium source:
branch: firmware-gnawty-5216.239.B
/src/soc/intel/baytrail/baytrail/gpio.h#418
/src/mainboard/google/gnawty/romstage.c#60
Test: boot 4GB Candy board and observe correct RAM id, amount detected
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia648846f4cdf65908db9a310b201562f0ff72951
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 474a7c51ce
Original-Change-Id: I8823c27385f4422184b5afa57f6048f7ff2a25ab
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18309
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/443676
Those are the result from tracing what linux or the option rom do
but are not needed here.
TESTED on Thinkpad X60.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4aa3ebf50bc772ff0baf0b6c685022ea40750234
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: d81078d944
Original-Change-Id: I4297a78c4ab6a19ef6161778c993fc3f3fb08c7e
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18294
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/443675
Kernel relies on FADT 8042 flag to enable/disable
8042 interface. If FADT reports 8042 capability and
8042 (/PS2) capability is actually disabled by coreboot,
kernel would assume the presence of 8042 based on the
FADT flag. This results in undesired system power off when
kernel tries to access the 8042 memory region. To address
this, CONFIG_NO_FADT_8042 was added to selectively
disable 8042 on FADT.
BUG=chrome-os-partner:61858
TEST=Boot OS and verify FADT 8042 flag
Change-Id: I45e667950850209b33531dbb7ed784f073648e69
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 2864f85725
Original-Change-Id: Ic80b3835cb5cccdde1203e24a58e28746b0196fc
Original-Signed-off-by: Jenny TC <jenny.tc@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18307
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/443672
Commit-Ready: Jenny Tc <jenny.tc@intel.com>
