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UPSTREAM: soc/intel/skylake: add PrmrrSize to chip config

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Prmrr configuration is supported by Kabylake FSP-M with UPD provided.
It is required as one of the SGX initialization steps in BIOS.

BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified uncore PRMRR MSRs get programmed to set
size and boot.

Change-Id: I4bf81697e1fa2a2329b67d1b228a329c3a42fc3e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e65affa2ed
Original-Change-Id: I2b3dc7c92487505165ee429bd1a37bd60ceac8f3
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18361
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445129
This commit is contained in:
Robbie Zhang 2017-02-13 12:07:53 -08:00 • committed by chrome-bot
commit ab587a2a96
2 changed files with 9 additions and 0 deletions
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8
src/soc/intel/skylake/chip.h
View file

@ -376,6 +376,14 @@ struct soc_intel_skylake_config {
/* Enable/Disable VMX feature */
u8 VmxEnable;
/*
* PRMRR size setting with three options
* 0x02000000 - 32MiB
* 0x04000000 - 64MiB
* 0x08000000 - 128MiB
*/
u32 PrmrrSize;
/* Statically clock gate 8254 PIT. */
u8 clock_gate_8254;

1
src/soc/intel/skylake/romstage/romstage_fsp20.c
View file

@ -139,6 +139,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
m_cfg->RMT = config->Rmt;
m_cfg->DdrFreqLimit = config->DdrFreqLimit;
m_cfg->VmxEnable = config->VmxEnable;
m_cfg->PrmrrSize = config->PrmrrSize;
for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
if (config->PcieRpEnable[i])
mask |= (1<<i);