diff --git a/src/northbridge/intel/haswell/Makefile.mk b/src/northbridge/intel/haswell/Makefile.mk
index bc8cf42046..c5cc82fc16 100644
--- a/src/northbridge/intel/haswell/Makefile.mk
+++ b/src/northbridge/intel/haswell/Makefile.mk
@@ -20,6 +20,10 @@ romstage-y += raminit_shared.c
 
 postcar-y += memmap.c
 
+ifneq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
+romstage-y += early_peg.c
+endif
+
 ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
 romstage-y += early_dmi.c early_pcie.c vcu_mailbox.c
 subdirs-y  += native_raminit
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 386c2897cc..d52a9d1b85 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -8,8 +8,6 @@
 
 #include "haswell.h"
 
-static bool peg_hidden[MAX_PEG_FUNC];
-
 static void haswell_setup_bars(void)
 {
 	printk(BIOS_DEBUG, "Setting up static northbridge registers...");
@@ -64,78 +62,6 @@ static void haswell_setup_igd(void)
 	pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02);
 }
 
-static void start_peg2_link_training(const pci_devfn_t dev)
-{
-	u32 mask;
-
-	switch (dev) {
-	case PCI_DEV(0, 1, 2):
-		mask = DEVEN_D1F2EN;
-		break;
-	case PCI_DEV(0, 1, 1):
-		mask = DEVEN_D1F1EN;
-		break;
-	case PCI_DEV(0, 1, 0):
-		mask = DEVEN_D1F0EN;
-		break;
-	default:
-		printk(BIOS_ERR, "Link training tried on a non-PEG device!\n");
-		return;
-	}
-
-	pci_update_config32(dev, 0xc24, ~(1 << 16), 1 << 5);
-	printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev)));
-
-	/*
-	 * The MRC will perform PCI enumeration, and if it detects a VGA
-	 * device in a PEG slot, it will disable the IGD and not reserve
-	 * any memory for it. Since the memory map is locked by the time
-	 * MRC finishes, the IGD can't be enabled afterwards. Wonderful.
-	 *
-	 * If one really wants to enable the Intel iGPU as primary, hide
-	 * all PEG devices during MRC execution. This will trick the MRC
-	 * into thinking there aren't any, and will enable the IGD. Note
-	 * that PEG AFE settings will not be programmed, which may cause
-	 * stability problems at higher PCIe link speeds. The most ideal
-	 * way to fix this problem for good is to implement native init.
-	 */
-	if (CONFIG(HASWELL_HIDE_PEG_FROM_MRC)) {
-		pci_update_config32(HOST_BRIDGE, DEVEN, ~mask, 0);
-		peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true;
-		printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n",
-		       PCI_FUNC(PCI_DEV2DEVFN(dev)));
-	}
-}
-
-void haswell_unhide_peg(void)
-{
-	u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
-
-	for (u8 fn = 0; fn < MAX_PEG_FUNC; fn++) {
-		if (peg_hidden[fn]) {
-			deven |= DEVEN_D1F0EN >> fn;
-			peg_hidden[fn] = false;
-			printk(BIOS_DEBUG, "Unhiding PEG1%d.\n", fn);
-		}
-	}
-
-	pci_write_config32(HOST_BRIDGE, DEVEN, deven);
-}
-
-static void haswell_setup_peg(void)
-{
-	u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
-
-	if (deven & DEVEN_D1F2EN)
-		start_peg2_link_training(PCI_DEV(0, 1, 2));
-
-	if (deven & DEVEN_D1F1EN)
-		start_peg2_link_training(PCI_DEV(0, 1, 1));
-
-	if (deven & DEVEN_D1F0EN)
-		start_peg2_link_training(PCI_DEV(0, 1, 0));
-}
-
 static void haswell_setup_misc(void)
 {
 	u32 reg32;
@@ -188,7 +114,9 @@ void haswell_early_initialization(void)
 	/* Setup IOMMU BARs */
 	haswell_setup_iommu();
 
-	haswell_setup_peg();
+	if (!CONFIG(INTEL_LYNXPOINT_LP))
+		northbridge_setup_peg();
+
 	haswell_setup_igd();
 
 	haswell_setup_misc();
diff --git a/src/northbridge/intel/haswell/early_peg.c b/src/northbridge/intel/haswell/early_peg.c
new file mode 100644
index 0000000000..4be9994629
--- /dev/null
+++ b/src/northbridge/intel/haswell/early_peg.c
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+static bool peg_hidden[MAX_PEG_FUNC];
+
+static void start_peg2_link_training(const pci_devfn_t dev)
+{
+	u32 mask;
+
+	switch (dev) {
+	case PCI_DEV(0, 1, 2):
+		mask = DEVEN_D1F2EN;
+		break;
+	case PCI_DEV(0, 1, 1):
+		mask = DEVEN_D1F1EN;
+		break;
+	case PCI_DEV(0, 1, 0):
+		mask = DEVEN_D1F0EN;
+		break;
+	default:
+		printk(BIOS_ERR, "Link training tried on a non-PEG device!\n");
+		return;
+	}
+
+	pci_update_config32(dev, 0xc24, ~(1 << 16), 1 << 5);
+	printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev)));
+
+	/*
+	 * The MRC will perform PCI enumeration, and if it detects a VGA
+	 * device in a PEG slot, it will disable the IGD and not reserve
+	 * any memory for it. Since the memory map is locked by the time
+	 * MRC finishes, the IGD can't be enabled afterwards. Wonderful.
+	 *
+	 * If one really wants to enable the Intel iGPU as primary, hide
+	 * all PEG devices during MRC execution. This will trick the MRC
+	 * into thinking there aren't any, and will enable the IGD. Note
+	 * that PEG AFE settings will not be programmed, which may cause
+	 * stability problems at higher PCIe link speeds. The most ideal
+	 * way to fix this problem for good is to implement native init.
+	 */
+	if (CONFIG(HASWELL_HIDE_PEG_FROM_MRC)) {
+		pci_update_config32(HOST_BRIDGE, DEVEN, ~mask, 0);
+		peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true;
+		printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n",
+		       PCI_FUNC(PCI_DEV2DEVFN(dev)));
+	}
+}
+
+void northbridge_unhide_peg(void)
+{
+	u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
+
+	for (u8 fn = 0; fn < MAX_PEG_FUNC; fn++) {
+		if (peg_hidden[fn]) {
+			deven |= DEVEN_D1F0EN >> fn;
+			peg_hidden[fn] = false;
+			printk(BIOS_DEBUG, "Unhiding PEG1%d.\n", fn);
+		}
+	}
+
+	pci_write_config32(HOST_BRIDGE, DEVEN, deven);
+}
+
+void northbridge_setup_peg(void)
+{
+	u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
+
+	if (deven & DEVEN_D1F2EN)
+		start_peg2_link_training(PCI_DEV(0, 1, 2));
+
+	if (deven & DEVEN_D1F1EN)
+		start_peg2_link_training(PCI_DEV(0, 1, 1));
+
+	if (deven & DEVEN_D1F0EN)
+		start_peg2_link_training(PCI_DEV(0, 1, 0));
+}
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index bd271f4b06..aeedd421e1 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -37,7 +37,9 @@ void mb_late_romstage_setup(void); /* optional */
 
 void haswell_early_initialization(void);
 void haswell_late_initialization(void);
-void haswell_unhide_peg(void);
+
+void northbridge_setup_peg(void);
+void northbridge_unhide_peg(void);
 
 void dmi_early_init(void);
 void peg_dmi_recipe(const bool is_peg, const pci_devfn_t dev);
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index 85fe967c7d..a6726f7f06 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -56,7 +56,8 @@ void mainboard_romstage_entry(void)
 		txt_dump_regions();
 	}
 
-	haswell_unhide_peg();
+	if (!CONFIG(INTEL_LYNXPOINT_LP))
+		northbridge_unhide_peg();
 
 	romstage_handoff_init(s3resume);