vendorcode/amd/fsp/glinda: Update FSP UPDs
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I6162d3a8c71765ea1863eca4c875c2c672060a76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/90418 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph
Felix Held
parent
244e8edf18
commit
f68450e39b
2 changed files with 138 additions and 3 deletions
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@ -98,7 +98,31 @@ typedef struct __packed {
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/** Offset 0x04D7**/ uint8_t UnusedUpdSpace1;
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/* usb_phy_ptr is actually struct usb_phy_config *, but that won't work for 64bit coreboot */
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/** Offset 0x04D8**/ uint32_t usb_phy_ptr;
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/** Offset 0x04DC**/ uint8_t UnusedUpdSpace2[292];
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/** Offset 0x04DC**/ uint8_t Usb4Rt0En;
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/** Offset 0x04DD**/ uint8_t Usb4Rt1En;
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/** Offset 0x04DE**/ uint8_t Usb4Rt0XhciEn;
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/** Offset 0x04DF**/ uint8_t Usb4Rt1XhciEn;
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/** Offset 0x04E0**/ uint64_t xgbe_port0_mac;
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/** Offset 0x04E8**/ uint64_t xgbe_port1_mac;
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/** Offset 0x04F0**/ uint8_t xgbe_port0_config_en;
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/** Offset 0x04F1**/ uint8_t xgbe_port1_config_en;
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/* xgbe_port0_table_ptr is actually uint32_t *, but that won't work for 64bit coreboot */
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/** Offset 0x04F2**/ uint32_t xgbe_port0_table_ptr;
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/** Offset 0x04F6**/ uint32_t xgbe_port1_table_ptr;
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/** Offset 0x04FA**/ uint8_t XgbeDisable;
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/** Offset 0x04FB**/ uint8_t disp_combo_PHY;
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/** Offset 0x04FC**/ uint8_t xgbe_led_en;
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/** Offset 0x04FD**/ uint8_t xgbe_led_link_status0;
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/** Offset 0x04FE**/ uint8_t xgbe_led_link_status1;
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/** Offset 0x04FF**/ uint8_t xgbe_led_link_speed0;
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/** Offset 0x0500**/ uint8_t xgbe_led_link_speed1;
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/** Offset 0x0501**/ uint8_t xgbe_led_tx_rx_blink_rate0;
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/** Offset 0x0502**/ uint8_t xgbe_led_tx_rx_blink_rate1;
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/** Offset 0x0503**/ uint32_t fch_rt_device_enable_map;
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/** Offset 0x0507**/ uint8_t amd_pcie_aer_report_mechanism;
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/** Offset 0x0508**/ uint8_t amd_nbio_ras_controlv2;
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/** Offset 0x0509**/ uint8_t pcie_ecrc_enablement;
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/** Offset 0x050A**/ uint8_t UnusedUpdSpace2[246];
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/** Offset 0x0600**/ uint16_t UpdTerminator;
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} FSP_M_CONFIG;
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@ -32,6 +32,7 @@ enum dxio_link_speed_cap {
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GEN1,
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GEN2,
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GEN3,
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GEN4,
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GEN_INVALID // Max Gen for boundary check
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};
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@ -199,7 +200,7 @@ typedef struct __packed {
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uint32_t reserved_3 :7;
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uint32_t device_number :5; // Desired root port device number
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uint32_t function_number :3; // Desired root port function number
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uint32_t link_speed_capability :2; // See dxio_link_speed_cap
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uint32_t :2;
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uint32_t auto_spd_change :2; // See dxio_upstream_auto_speed_change
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uint32_t eq_preset :4; // Gen3 equalization preset
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uint32_t link_aspm :2; // See dxio_aspm_type
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@ -209,7 +210,8 @@ typedef struct __packed {
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uint8_t link_hotplug; // See dxio_link_hotplug_type
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uint8_t slot_power_limit; // Currently unused by FSP
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uint32_t slot_power_limit_scale :2; // Currently unused by FSP
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uint32_t reserved_4 :6;
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uint32_t link_speed_capability :3; // See dxio_link_speed_cap
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uint32_t :3;
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uint32_t link_compliance_mode :1; // Currently unused by FSP
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uint32_t link_safe_mode :1; // Currently unused by FSP
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uint32_t sb_link :1; // Currently unused by FSP
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@ -221,4 +223,113 @@ typedef struct __packed {
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uint16_t port_params[NUM_DXIO_PORT_PARAMS*2]; // key-value parameters. see dxio_port_param_type
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} fsp_dxio_descriptor;
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typedef enum {
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XGBE_PORT_DISABLE,
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XGBE_PORT_ENABLE,
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} xgbe_port_enable;
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typedef enum {
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XGBE_PHY_MODE_RJ45,
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XGBE_PHY_MODE_SFP_PLUS,
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XGBE_PHY_MODE_BACKPLANE
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} xgbe_port_phy_modes;
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typedef enum {
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XGBE_RESERVED,
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XGBE_10G_1G_BACKPLANE,
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XGBE_2_5G_BACKPLANE,
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XGBE_SOLDERED_DOWN_1000BASE_T,
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XGBE_SOLDERED_DOWN_1000BASE_X,
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XGBE_SOLDERED_DOWN_NBASE_T,
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XGBE_SOLDERED_DOWN_10GBASE_T,
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XGBE_SOLDERED_DOWN_10GBASE_R,
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XGBE_SFP_PLUS_CONNECTOR,
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XGBE_PORT_SGMII_BACKPLANE,
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XGBE_5G_BACKPLANE,
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} xgbe_port_platform_config;
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typedef enum {
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XGBE_PORT_SPEED_10M = 0x1,
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XGBE_PORT_SPEED_100M = 0x2,
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XGBE_PORT_SPEED_1G = 0x4,
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XGBE_PORT_SPEED_2500M = 0x8,
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XGBE_PORT_SPEED_5G = 0x32,
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XGBE_PORT_SPEED_10G = 0x10,
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XGBE_PORT_SPEED_10_100_1000M = 0x7,
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} xgbe_port_speed_config;
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typedef enum {
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XGBE_PORT_NOT_USED = 0x0,
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XGBE_SFP_PLUS_CONNECTION = 0x1,
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XGBE_CONNECTION_MDIO_PHY = 0x2,
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XGBE_BACKPLANE_CONNECTION = 0x4,
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} xgbe_port_connection_type;
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struct __packed xgbe_port_table {
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uint8_t XgbePortConfig; ///< XGbE controller Port Config Enable/disable
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uint8_t XgbePortPlatformConfig; ///< Platform Config
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/// @li <b>0000</b> - Reserved
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/// @li <b>0001</b> - 10G/1G Backplane
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/// @li <b>0010</b> - 2.5G Backplane
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/// @li <b>0011</b> - 1000Base-T
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/// @li <b>0100</b> - 1000Base-X
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/// @li <b>0101</b> - NBase-T
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/// @li <b>0110</b> - 10GBase-T
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/// @li <b>0111</b> - 10GBase-X
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/// @li <b>1000</b> - SFP+
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uint8_t XgbePortSupportedSpeed; ///< Indicated Ethernet speeds supported on platform
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/// @li <b>1xxx</b> - 10/100/1000M
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/// @li <b>x1xx</b> - 1G
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/// @li <b>xx1x</b> - 1G
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/// @li <b>xxx1</b> - 100M
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uint8_t XgbePortConnectedType; ///< PHY connected type
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/// @li <b>000</b> - Port not used
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/// @li <b>001</b> - SFP+
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/// @li <b>010</b> - MDIO
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/// @li <b>100</b> - Backplane connection
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uint8_t XgbePortMdioId; ///< MDIO ID of the PHY associated with this port
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uint8_t XgbePortMdioResetType; ///< MDIO PHY reset type
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/// @li <b>00</b> - None
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/// @li <b>01</b> - I2C GPIO
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/// @li <b>10</b> - Integrated GPIO
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/// @li <b>11</b> - Reserved
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uint8_t XgbePortResetGpioNum; ///< GPIO used to control the reset
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uint8_t XgbePortMdioResetI2cAddress; ///< I2C address of PCA9535 MDIO reset GPIO
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uint8_t XgbePortSfpI2cAddress; ///< I2C address of PCA9535 for SFP
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uint8_t XgbePortSfpTxFaultGpio; ///< GPIO number for SFP+ TX_FAULT
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uint8_t XgbePortSfpRsGpio; ///< GPIO number for SFP+ RS
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uint8_t XgbePortSfpModAbsGpio; ///< GPIO number for SFP+ Mod_ABS
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uint8_t XgbePortSfpRxLosGpio; ///< GPIO number for SFP+ Rx_LOS
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uint8_t XgbePortSfpGpioMask; ///< GPIO Mask for SFP+
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/// @li <b>1xxx</b> - Rx_LOS not supported
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/// @li <b>x1xx</b> - Mod_ABS not supported
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/// @li <b>xx1x</b> - RS not supported
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/// @li <b>xxx1</b> - TX_FAULT not supported
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uint8_t XgbePortSfpTwiAddress; ///< Address of PCA9545 I2C multiplexor
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uint8_t XgbePortSfpTwiBus; ///< Downstream channel of PCA9545
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uint8_t XgbaPortRedriverPresent; ///< Redriver Present or not
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uint8_t Reserve0[3]; ///< Reserved
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uint8_t XgbaPortRedriverModel; ///< Redriver Model
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/// @li <b>00</b> - InPhi 4223
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/// @li <b>01</b> - InPhi 4227
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uint8_t XgbaPortRedriverInterface; ///< Redriver Interface
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/// @li <b>00</b> - MDIO
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/// @li <b>01</b> - I2C
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uint8_t XgbaPortRedriverAddress; ///< Redriver Address
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uint8_t XgbaPortRedriverLane; ///< Redriver Lane
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uint8_t XgbaPortPadGpio; ///< Portx_GPIO Pad selection
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/// @li <b>001</b> - MDIO0 pin
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/// @li <b>010</b> - MDIO1 pin
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/// @li <b>100</b> - SFP pin
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uint8_t XgbaPortPadMdio; ///< Portx_Mdio Pad selection
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/// @li <b>001</b> - MDIO0 pin
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/// @li <b>010</b> - MDIO1 pin
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/// @li <b>100</b> - SFP pin
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uint8_t XgbaPortPadI2C; ///< Portx_I2C Pad selection
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/// @li <b>001</b> - MDIO0 pin
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/// @li <b>010</b> - MDIO1 pin
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/// @li <b>100</b> - SFP pin
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uint8_t Reserve1; ///< Reserved
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};
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#endif /* PI_PLATFORM_DESCRIPTORS_H */
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