diff --git a/src/vendorcode/amd/fsp/glinda/FspmUpd.h b/src/vendorcode/amd/fsp/glinda/FspmUpd.h
index 60a00b2bd0..4475a69180 100644
--- a/src/vendorcode/amd/fsp/glinda/FspmUpd.h
+++ b/src/vendorcode/amd/fsp/glinda/FspmUpd.h
@@ -98,7 +98,31 @@ typedef struct __packed {
/** Offset 0x04D7**/ uint8_t UnusedUpdSpace1;
/* usb_phy_ptr is actually struct usb_phy_config *, but that won't work for 64bit coreboot */
/** Offset 0x04D8**/ uint32_t usb_phy_ptr;
- /** Offset 0x04DC**/ uint8_t UnusedUpdSpace2[292];
+ /** Offset 0x04DC**/ uint8_t Usb4Rt0En;
+ /** Offset 0x04DD**/ uint8_t Usb4Rt1En;
+ /** Offset 0x04DE**/ uint8_t Usb4Rt0XhciEn;
+ /** Offset 0x04DF**/ uint8_t Usb4Rt1XhciEn;
+ /** Offset 0x04E0**/ uint64_t xgbe_port0_mac;
+ /** Offset 0x04E8**/ uint64_t xgbe_port1_mac;
+ /** Offset 0x04F0**/ uint8_t xgbe_port0_config_en;
+ /** Offset 0x04F1**/ uint8_t xgbe_port1_config_en;
+ /* xgbe_port0_table_ptr is actually uint32_t *, but that won't work for 64bit coreboot */
+ /** Offset 0x04F2**/ uint32_t xgbe_port0_table_ptr;
+ /** Offset 0x04F6**/ uint32_t xgbe_port1_table_ptr;
+ /** Offset 0x04FA**/ uint8_t XgbeDisable;
+ /** Offset 0x04FB**/ uint8_t disp_combo_PHY;
+ /** Offset 0x04FC**/ uint8_t xgbe_led_en;
+ /** Offset 0x04FD**/ uint8_t xgbe_led_link_status0;
+ /** Offset 0x04FE**/ uint8_t xgbe_led_link_status1;
+ /** Offset 0x04FF**/ uint8_t xgbe_led_link_speed0;
+ /** Offset 0x0500**/ uint8_t xgbe_led_link_speed1;
+ /** Offset 0x0501**/ uint8_t xgbe_led_tx_rx_blink_rate0;
+ /** Offset 0x0502**/ uint8_t xgbe_led_tx_rx_blink_rate1;
+ /** Offset 0x0503**/ uint32_t fch_rt_device_enable_map;
+ /** Offset 0x0507**/ uint8_t amd_pcie_aer_report_mechanism;
+ /** Offset 0x0508**/ uint8_t amd_nbio_ras_controlv2;
+ /** Offset 0x0509**/ uint8_t pcie_ecrc_enablement;
+ /** Offset 0x050A**/ uint8_t UnusedUpdSpace2[246];
/** Offset 0x0600**/ uint16_t UpdTerminator;
} FSP_M_CONFIG;
diff --git a/src/vendorcode/amd/fsp/glinda/platform_descriptors.h b/src/vendorcode/amd/fsp/glinda/platform_descriptors.h
index b214e915a9..c627517d6b 100644
--- a/src/vendorcode/amd/fsp/glinda/platform_descriptors.h
+++ b/src/vendorcode/amd/fsp/glinda/platform_descriptors.h
@@ -32,6 +32,7 @@ enum dxio_link_speed_cap {
GEN1,
GEN2,
GEN3,
+ GEN4,
GEN_INVALID // Max Gen for boundary check
};
@@ -199,7 +200,7 @@ typedef struct __packed {
uint32_t reserved_3 :7;
uint32_t device_number :5; // Desired root port device number
uint32_t function_number :3; // Desired root port function number
- uint32_t link_speed_capability :2; // See dxio_link_speed_cap
+ uint32_t :2;
uint32_t auto_spd_change :2; // See dxio_upstream_auto_speed_change
uint32_t eq_preset :4; // Gen3 equalization preset
uint32_t link_aspm :2; // See dxio_aspm_type
@@ -209,7 +210,8 @@ typedef struct __packed {
uint8_t link_hotplug; // See dxio_link_hotplug_type
uint8_t slot_power_limit; // Currently unused by FSP
uint32_t slot_power_limit_scale :2; // Currently unused by FSP
- uint32_t reserved_4 :6;
+ uint32_t link_speed_capability :3; // See dxio_link_speed_cap
+ uint32_t :3;
uint32_t link_compliance_mode :1; // Currently unused by FSP
uint32_t link_safe_mode :1; // Currently unused by FSP
uint32_t sb_link :1; // Currently unused by FSP
@@ -221,4 +223,113 @@ typedef struct __packed {
uint16_t port_params[NUM_DXIO_PORT_PARAMS*2]; // key-value parameters. see dxio_port_param_type
} fsp_dxio_descriptor;
+typedef enum {
+ XGBE_PORT_DISABLE,
+ XGBE_PORT_ENABLE,
+} xgbe_port_enable;
+
+typedef enum {
+ XGBE_PHY_MODE_RJ45,
+ XGBE_PHY_MODE_SFP_PLUS,
+ XGBE_PHY_MODE_BACKPLANE
+} xgbe_port_phy_modes;
+
+typedef enum {
+ XGBE_RESERVED,
+ XGBE_10G_1G_BACKPLANE,
+ XGBE_2_5G_BACKPLANE,
+ XGBE_SOLDERED_DOWN_1000BASE_T,
+ XGBE_SOLDERED_DOWN_1000BASE_X,
+ XGBE_SOLDERED_DOWN_NBASE_T,
+ XGBE_SOLDERED_DOWN_10GBASE_T,
+ XGBE_SOLDERED_DOWN_10GBASE_R,
+ XGBE_SFP_PLUS_CONNECTOR,
+ XGBE_PORT_SGMII_BACKPLANE,
+ XGBE_5G_BACKPLANE,
+} xgbe_port_platform_config;
+
+typedef enum {
+ XGBE_PORT_SPEED_10M = 0x1,
+ XGBE_PORT_SPEED_100M = 0x2,
+ XGBE_PORT_SPEED_1G = 0x4,
+ XGBE_PORT_SPEED_2500M = 0x8,
+ XGBE_PORT_SPEED_5G = 0x32,
+ XGBE_PORT_SPEED_10G = 0x10,
+ XGBE_PORT_SPEED_10_100_1000M = 0x7,
+} xgbe_port_speed_config;
+
+typedef enum {
+ XGBE_PORT_NOT_USED = 0x0,
+ XGBE_SFP_PLUS_CONNECTION = 0x1,
+ XGBE_CONNECTION_MDIO_PHY = 0x2,
+ XGBE_BACKPLANE_CONNECTION = 0x4,
+} xgbe_port_connection_type;
+
+struct __packed xgbe_port_table {
+ uint8_t XgbePortConfig; ///< XGbE controller Port Config Enable/disable
+ uint8_t XgbePortPlatformConfig; ///< Platform Config
+ /// @li 0000 - Reserved
+ /// @li 0001 - 10G/1G Backplane
+ /// @li 0010 - 2.5G Backplane
+ /// @li 0011 - 1000Base-T
+ /// @li 0100 - 1000Base-X
+ /// @li 0101 - NBase-T
+ /// @li 0110 - 10GBase-T
+ /// @li 0111 - 10GBase-X
+ /// @li 1000 - SFP+
+ uint8_t XgbePortSupportedSpeed; ///< Indicated Ethernet speeds supported on platform
+ /// @li 1xxx - 10/100/1000M
+ /// @li x1xx - 1G
+ /// @li xx1x - 1G
+ /// @li xxx1 - 100M
+ uint8_t XgbePortConnectedType; ///< PHY connected type
+ /// @li 000 - Port not used
+ /// @li 001 - SFP+
+ /// @li 010 - MDIO
+ /// @li 100 - Backplane connection
+ uint8_t XgbePortMdioId; ///< MDIO ID of the PHY associated with this port
+ uint8_t XgbePortMdioResetType; ///< MDIO PHY reset type
+ /// @li 00 - None
+ /// @li 01 - I2C GPIO
+ /// @li 10 - Integrated GPIO
+ /// @li 11 - Reserved
+ uint8_t XgbePortResetGpioNum; ///< GPIO used to control the reset
+ uint8_t XgbePortMdioResetI2cAddress; ///< I2C address of PCA9535 MDIO reset GPIO
+ uint8_t XgbePortSfpI2cAddress; ///< I2C address of PCA9535 for SFP
+ uint8_t XgbePortSfpTxFaultGpio; ///< GPIO number for SFP+ TX_FAULT
+ uint8_t XgbePortSfpRsGpio; ///< GPIO number for SFP+ RS
+ uint8_t XgbePortSfpModAbsGpio; ///< GPIO number for SFP+ Mod_ABS
+ uint8_t XgbePortSfpRxLosGpio; ///< GPIO number for SFP+ Rx_LOS
+ uint8_t XgbePortSfpGpioMask; ///< GPIO Mask for SFP+
+ /// @li 1xxx - Rx_LOS not supported
+ /// @li x1xx - Mod_ABS not supported
+ /// @li xx1x - RS not supported
+ /// @li xxx1 - TX_FAULT not supported
+ uint8_t XgbePortSfpTwiAddress; ///< Address of PCA9545 I2C multiplexor
+ uint8_t XgbePortSfpTwiBus; ///< Downstream channel of PCA9545
+ uint8_t XgbaPortRedriverPresent; ///< Redriver Present or not
+ uint8_t Reserve0[3]; ///< Reserved
+ uint8_t XgbaPortRedriverModel; ///< Redriver Model
+ /// @li 00 - InPhi 4223
+ /// @li 01 - InPhi 4227
+ uint8_t XgbaPortRedriverInterface; ///< Redriver Interface
+ /// @li 00 - MDIO
+ /// @li 01 - I2C
+ uint8_t XgbaPortRedriverAddress; ///< Redriver Address
+ uint8_t XgbaPortRedriverLane; ///< Redriver Lane
+ uint8_t XgbaPortPadGpio; ///< Portx_GPIO Pad selection
+ /// @li 001 - MDIO0 pin
+ /// @li 010 - MDIO1 pin
+ /// @li 100 - SFP pin
+ uint8_t XgbaPortPadMdio; ///< Portx_Mdio Pad selection
+ /// @li 001 - MDIO0 pin
+ /// @li 010 - MDIO1 pin
+ /// @li 100 - SFP pin
+ uint8_t XgbaPortPadI2C; ///< Portx_I2C Pad selection
+ /// @li 001 - MDIO0 pin
+ /// @li 010 - MDIO1 pin
+ /// @li 100 - SFP pin
+ uint8_t Reserve1; ///< Reserved
+ };
+
#endif /* PI_PLATFORM_DESCRIPTORS_H */