From f61ffb68c985f4f3bdb3832e8c1daafc2975ec6b Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Wed, 24 Sep 2025 14:23:33 -0700 Subject: [PATCH] soc/intel/pantherlake: Remove unused TxDqDqs retraining parameter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit removes the unused `lp_ddr_dq_dqs_re_training` field from various memory configuration structures across multiple mainboard variants, including google/fatcat, google/ocelot, and intel/ptlrvp. This change should reduce complexity and prevent unnecessary memory operations related to DQ/DQS retraining. Write DqDqs retraining is enabled in Intel FSP by default. This can be verified with debug FSP logs by checking WRTRETRAIN and "MRC task -- Write DQ/DQS Retraining -- Started." prints. BUG=None TEST=Boot to OS on google fatcat board and verify DQ/DQS retraining. Change-Id: Ib298b06260f576bee1f078dc09b1e23a9772b431 Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/c/coreboot/+/89334 Reviewed-by: Jérémy Compostella Reviewed-by: Subrata Banik Reviewed-by: Zhixing Ma Tested-by: build bot (Jenkins) --- src/mainboard/google/fatcat/variants/fatcat/memory.c | 2 -- src/mainboard/google/fatcat/variants/felino/memory.c | 2 -- src/mainboard/google/fatcat/variants/francka/memory.c | 2 -- src/mainboard/google/fatcat/variants/kinmen/memory.c | 2 -- src/mainboard/google/fatcat/variants/lapis/memory.c | 2 -- src/mainboard/google/fatcat/variants/moonstone/memory.c | 2 -- src/mainboard/google/ocelot/variants/matsu/memory.c | 2 -- src/mainboard/google/ocelot/variants/ocelot/memory.c | 4 ---- src/mainboard/google/ocelot/variants/ojal/memory.c | 2 -- src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c | 8 -------- src/soc/intel/pantherlake/include/soc/meminit.h | 3 --- 11 files changed, 31 deletions(-) diff --git a/src/mainboard/google/fatcat/variants/fatcat/memory.c b/src/mainboard/google/fatcat/variants/fatcat/memory.c index e0908adabd..414d3998c9 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/memory.c +++ b/src/mainboard/google/fatcat/variants/fatcat/memory.c @@ -55,8 +55,6 @@ static const struct mb_cfg lp5_mem_config = { .ect = true, /* Early Command Training */ - .lp_ddr_dq_dqs_re_training = 1, - .user_bd = BOARD_TYPE_ULT_ULX, .lp5x_config = { diff --git a/src/mainboard/google/fatcat/variants/felino/memory.c b/src/mainboard/google/fatcat/variants/felino/memory.c index e0908adabd..414d3998c9 100644 --- a/src/mainboard/google/fatcat/variants/felino/memory.c +++ b/src/mainboard/google/fatcat/variants/felino/memory.c @@ -55,8 +55,6 @@ static const struct mb_cfg lp5_mem_config = { .ect = true, /* Early Command Training */ - .lp_ddr_dq_dqs_re_training = 1, - .user_bd = BOARD_TYPE_ULT_ULX, .lp5x_config = { diff --git a/src/mainboard/google/fatcat/variants/francka/memory.c b/src/mainboard/google/fatcat/variants/francka/memory.c index c5b8165ca4..d7f331f25c 100644 --- a/src/mainboard/google/fatcat/variants/francka/memory.c +++ b/src/mainboard/google/fatcat/variants/francka/memory.c @@ -55,8 +55,6 @@ static const struct mb_cfg lp5_mem_config = { .ect = true, /* Early Command Training */ - .lp_ddr_dq_dqs_re_training = 1, - .user_bd = BOARD_TYPE_ULT_ULX, .lp5x_config = { diff --git a/src/mainboard/google/fatcat/variants/kinmen/memory.c b/src/mainboard/google/fatcat/variants/kinmen/memory.c index 4637347562..b62eb34261 100644 --- a/src/mainboard/google/fatcat/variants/kinmen/memory.c +++ b/src/mainboard/google/fatcat/variants/kinmen/memory.c @@ -55,8 +55,6 @@ static const struct mb_cfg lp5_mem_config = { .ect = true, /* Early Command Training */ - .lp_ddr_dq_dqs_re_training = 1, - .user_bd = BOARD_TYPE_ULT_ULX, .lp5x_config = { diff --git a/src/mainboard/google/fatcat/variants/lapis/memory.c b/src/mainboard/google/fatcat/variants/lapis/memory.c index 0c2a4e79fd..2fddc62b40 100644 --- a/src/mainboard/google/fatcat/variants/lapis/memory.c +++ b/src/mainboard/google/fatcat/variants/lapis/memory.c @@ -55,8 +55,6 @@ static const struct mb_cfg lp5_mem_config = { .ect = true, /* Early Command Training */ - .lp_ddr_dq_dqs_re_training = 1, - .user_bd = BOARD_TYPE_ULT_ULX, .lp5x_config = { diff --git a/src/mainboard/google/fatcat/variants/moonstone/memory.c b/src/mainboard/google/fatcat/variants/moonstone/memory.c index 4637347562..b62eb34261 100644 --- a/src/mainboard/google/fatcat/variants/moonstone/memory.c +++ b/src/mainboard/google/fatcat/variants/moonstone/memory.c @@ -55,8 +55,6 @@ static const struct mb_cfg lp5_mem_config = { .ect = true, /* Early Command Training */ - .lp_ddr_dq_dqs_re_training = 1, - .user_bd = BOARD_TYPE_ULT_ULX, .lp5x_config = { diff --git a/src/mainboard/google/ocelot/variants/matsu/memory.c b/src/mainboard/google/ocelot/variants/matsu/memory.c index 59fa99f0eb..5bcb96121b 100644 --- a/src/mainboard/google/ocelot/variants/matsu/memory.c +++ b/src/mainboard/google/ocelot/variants/matsu/memory.c @@ -35,8 +35,6 @@ static const struct mb_cfg lp5_mem_config = { .ect = true, /* Early Command Training */ - .lp_ddr_dq_dqs_re_training = 1, - .user_bd = BOARD_TYPE_ULT_ULX, .lp5x_config = { diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory.c b/src/mainboard/google/ocelot/variants/ocelot/memory.c index 43f40a9629..4f0a78a088 100644 --- a/src/mainboard/google/ocelot/variants/ocelot/memory.c +++ b/src/mainboard/google/ocelot/variants/ocelot/memory.c @@ -39,8 +39,6 @@ static const struct mb_cfg lp5_mem_config = { .ect = true, /* Early Command Training */ - .lp_ddr_dq_dqs_re_training = 1, - .user_bd = BOARD_TYPE_ULT_ULX, .lp5x_config = { @@ -55,8 +53,6 @@ static const struct mb_cfg ddr5_mem_config = { .user_bd = BOARD_TYPE_ULT_ULX, - .lp_ddr_dq_dqs_re_training = 1, - .ddr_config = { .dq_pins_interleaved = false, }, diff --git a/src/mainboard/google/ocelot/variants/ojal/memory.c b/src/mainboard/google/ocelot/variants/ojal/memory.c index 1315639496..c36eadb60e 100644 --- a/src/mainboard/google/ocelot/variants/ojal/memory.c +++ b/src/mainboard/google/ocelot/variants/ojal/memory.c @@ -38,8 +38,6 @@ static const struct mb_cfg lp5_mem_config = { .ect = true, /* Early Command Training */ - .lp_ddr_dq_dqs_re_training = 1, - .user_bd = BOARD_TYPE_ULT_ULX, .lp5x_config = { diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c index 350405dc29..4882edb324 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c @@ -56,8 +56,6 @@ static const struct mb_cfg gcs_mem_config = { .ect = true, /* Early Command Training */ - .lp_ddr_dq_dqs_re_training = 1, - .user_bd = BOARD_TYPE_ULT_ULX, .lp5x_config = { @@ -116,8 +114,6 @@ static const struct mb_cfg lp5_t3_mem_config = { .ect = true, /* Early Command Training */ - .lp_ddr_dq_dqs_re_training = 1, - .user_bd = BOARD_TYPE_ULT_ULX, .lp5x_config = { @@ -176,8 +172,6 @@ static const struct mb_cfg lp5_t4_mem_config = { .ect = true, /* Early Command Training */ - .lp_ddr_dq_dqs_re_training = 1, - .user_bd = BOARD_TYPE_ULT_ULX, .lp5x_config = { @@ -196,8 +190,6 @@ static const struct mb_cfg ddr5_mem_config = { .user_bd = BOARD_TYPE_ULT_ULX, - .lp_ddr_dq_dqs_re_training = 1, - .ddr_config = { .dq_pins_interleaved = false, } diff --git a/src/soc/intel/pantherlake/include/soc/meminit.h b/src/soc/intel/pantherlake/include/soc/meminit.h index 7b72f9991c..63404f8c17 100644 --- a/src/soc/intel/pantherlake/include/soc/meminit.h +++ b/src/soc/intel/pantherlake/include/soc/meminit.h @@ -102,9 +102,6 @@ struct mb_cfg { /* Command Mirror */ uint8_t cmd_mirror; - - /* Enable/Disable TxDqDqs Retraining for LP5 */ - uint8_t lp_ddr_dq_dqs_re_training; }; void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,