From f415d2c0aaffc0f1a3592551a2db782d538f8f4f Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Fri, 18 Oct 2013 17:10:32 -0700 Subject: [PATCH] tegra124: fix clear_fifo_status() in SPI driver The bits in the mask are wrong now that we're using the #defines with all the bits shifted into place already (before it was just a number that needed shifting). BUG=none BRANCH=none TEST=built and booted on nyan, which isn't saying much since we aren't having FIFO issues. Still, this is a pretty obvious fix. Change-Id: Iddd52be8bf0f801afeb731a06befb5c9612ec8b1 Signed-off-by: David Hendricks Reviewed-on: https://chromium-review.googlesource.com/173738 Reviewed-by: Gabe Black Commit-Queue: Gabe Black --- src/soc/nvidia/tegra124/spi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 2a8c8bf537..15e9695955 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -300,11 +300,11 @@ static void dump_fifo_status(struct tegra_spi_channel *spi) static void clear_fifo_status(struct tegra_spi_channel *spi) { clrbits_le32(&spi->regs->fifo_status, - (SPI_FIFO_STATUS_ERR | - SPI_FIFO_STATUS_TX_FIFO_OVF | - SPI_FIFO_STATUS_TX_FIFO_UNR | - SPI_FIFO_STATUS_RX_FIFO_OVF | - SPI_FIFO_STATUS_RX_FIFO_UNR) << 4); + SPI_FIFO_STATUS_ERR | + SPI_FIFO_STATUS_TX_FIFO_OVF | + SPI_FIFO_STATUS_TX_FIFO_UNR | + SPI_FIFO_STATUS_RX_FIFO_OVF | + SPI_FIFO_STATUS_RX_FIFO_UNR); } static void dump_spi_regs(struct tegra_spi_channel *spi)