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Remove some remaining code inside #if 0.

Browse source 
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Builds and run to filo.
Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@596 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Carl-Daniel Hailfinger 2008-02-13 22:51:03 +00:00
commit f3ba6dc175
2 changed files with 0 additions and 30 deletions
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14
northbridge/amd/geodelx/geodelx.c
View file

@ -163,20 +163,6 @@ static void geodelx_northbridge_init(struct device *dev)
printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
enable_shadow(dev);
#if 0
/* Swiss cheese */
msr = rdmsr(MSR_GLIU0_SHADOW);
msr.hi |= 0x3;
msr.lo |= 0x30000;
printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
MSR_GLIU0_SHADOW, msr.hi, msr.lo);
printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
MSR_GLIU1_SHADOW, msr.hi, msr.lo);
/* TODO: Is the respective wrmsr() missing? */
#endif
}
/**

16
northbridge/amd/geodelx/raminit.c
View file

@ -216,15 +216,6 @@ static void check_ddr_max(u8 dimm0, u8 dimm1)
if (spd_byte1 == 0xFF)
spd_byte1 = 0;
/* I don't think you need this check. */
#if 0
if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0) {
printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink speed\n");
post_code(POST_PLL_MEM_FAIL);
hlt();
}
#endif
/* Use the slowest DIMM. */
if (spd_byte0 < spd_byte1)
spd_byte0 = spd_byte1;
@ -580,13 +571,6 @@ void sdram_set_registers(void)
msr.lo &= ~0xF0;
msr.lo |= 0x40; /* Set refresh to 4 SDRAM clocks. */
wrmsr(MC_CF07_DATA, msr);
/* Memory Interleave: Set HOI here otherwise default is LOI. */
#if 0
msr = rdmsr(MC_CF8F_DATA);
msr.hi |= CF8F_UPPER_HOI_LOI_SET;
wrmsr(MC_CF8F_DATA, msr);
#endif
}
/**