diff --git a/northbridge/amd/geodelx/geodelx.c b/northbridge/amd/geodelx/geodelx.c
index 4d8291035b..ca122d34cb 100644
--- a/northbridge/amd/geodelx/geodelx.c
+++ b/northbridge/amd/geodelx/geodelx.c
@@ -163,20 +163,6 @@ static void geodelx_northbridge_init(struct device *dev)
 	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
 
 	enable_shadow(dev);
-
-#if 0
-	/* Swiss cheese */
-	msr = rdmsr(MSR_GLIU0_SHADOW);
-
-	msr.hi |= 0x3;
-	msr.lo |= 0x30000;
-
-	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
-	       MSR_GLIU0_SHADOW, msr.hi, msr.lo);
-	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
-	       MSR_GLIU1_SHADOW, msr.hi, msr.lo);
-	/* TODO: Is the respective wrmsr() missing? */
-#endif
 }
 
 /**
diff --git a/northbridge/amd/geodelx/raminit.c b/northbridge/amd/geodelx/raminit.c
index 97127fb608..dfdd08b72f 100644
--- a/northbridge/amd/geodelx/raminit.c
+++ b/northbridge/amd/geodelx/raminit.c
@@ -216,15 +216,6 @@ static void check_ddr_max(u8 dimm0, u8 dimm1)
 	if (spd_byte1 == 0xFF)
 		spd_byte1 = 0;
 
-	/* I don't think you need this check. */
-#if 0
-	if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0) {
-		printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink speed\n");
-		post_code(POST_PLL_MEM_FAIL);
-		hlt();
-	}
-#endif
-
 	/* Use the slowest DIMM. */
 	if (spd_byte0 < spd_byte1)
 		spd_byte0 = spd_byte1;
@@ -580,13 +571,6 @@ void sdram_set_registers(void)
 	msr.lo &= ~0xF0;
 	msr.lo |= 0x40;		/* Set refresh to 4 SDRAM clocks. */
 	wrmsr(MC_CF07_DATA, msr);
-
-	/* Memory Interleave: Set HOI here otherwise default is LOI. */
-#if 0
-	msr = rdmsr(MC_CF8F_DATA);
-	msr.hi |= CF8F_UPPER_HOI_LOI_SET;
-	wrmsr(MC_CF8F_DATA, msr);
-#endif
 }
 
 /**