From f2d03a461a00a2b184c2a8771d8d2c893a97b22e Mon Sep 17 00:00:00 2001 From: Venkateswarlu Vinjamuri Date: Thu, 8 Sep 2016 15:25:35 -0700 Subject: [PATCH] UPSTREAM: mainboard/google/reef: Disable CLKREQ of unused PCIe root ports 1. Removes PCIe blocker for S0ix. 2. Set the correct PCIe root port for wifi/bt on EVT. 3. Turn off CLKREQs of unused PCIe root ports to power gate the IP. BUG=None BRANCH=None TEST=None Signed-off-by: Venkateswarlu Vinjamuri Reviewed-on: https://review.coreboot.org/16557 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Change-Id: Iefd8869688d3a44b435dab9fc792275cd7f7e091 Reviewed-on: https://chromium-review.googlesource.com/384962 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- .../google/reef/variants/baseboard/devicetree.cb | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 2ac20de2dc..e663787ae2 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -4,7 +4,14 @@ chip soc/intel/apollolake device lapic 0 on end end - register "pcie_rp4_clkreq_pin" = "0" # wifi/bt + register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + # Disable unused clkreq of PCIe root ports + register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + # EMMC TX DATA Delay 1 # Refer to EDS-Vol2-22.3.