From f1d1c825dcbd6ad277e2dae883734eb2064b00b8 Mon Sep 17 00:00:00 2001 From: Kilian Krause Date: Fri, 21 Nov 2025 10:41:07 +0100 Subject: [PATCH] mb/siemens/mc_rpl1: Enable IBECC Enable In-band ECC (IBECC) for mc_rpl1. IBECC provides memory error detection and correction capabilities without requiring ECC memory modules. TEST=Inject correctable Error and verify IBECC detection and correction through system logs. Testing based on Intel Doc. #751401 Change-Id: Ibf2a61bf425a51762fa8bb1cfe7b6f57edd3cfb5 Signed-off-by: Kilian Krause Reviewed-on: https://review.coreboot.org/c/coreboot/+/90202 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer Reviewed-by: Uwe Poeche --- .../siemens/mc_rpl/variants/mc_rpl1/overridetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb index ae9f1c0ab4..ae514c2f3e 100644 --- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb +++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb @@ -17,6 +17,12 @@ chip soc/intel/alderlake [1] = 1, }" + # Enable IBECC for the complete memory + register "ibecc" = "{ + .enable = 1, + .mode = IBECC_MODE_ALL + }" + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Port1 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Port2 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Onboard USB