From f0ad05b57ebe41352467416d803aceeb4f538ec8 Mon Sep 17 00:00:00 2001 From: John Su Date: Mon, 12 May 2025 13:52:13 +0800 Subject: [PATCH] mb/google/brya/var/uldrenite: Fix USB_OC1 for USB3 A0 port According to the HW schematics, GPP_A14 should be set as USB_OC1 for the A0 port, but it was found that the USB3_A0 port did not match the configuration, so this has been corrected. BUG=b:410481989 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I2fcf15ca008eca6c74f4020c3fa7af8863a56a00 Signed-off-by: John Su Reviewed-on: https://review.coreboot.org/c/coreboot/+/87637 Reviewed-by: Dtrain Hsu Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/mainboard/google/brya/variants/uldrenite/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb index 78fec3dab2..8b17bd94c2 100644 --- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb @@ -91,7 +91,7 @@ chip soc/intel/alderlake register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # User Facing Camera register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # World Facing Camera - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"