Code changes from my work and the AMD760MP chipset.
The primary changes is the way in which printk works. But there are many other assorted code cleanups. Just look and see :)
This commit is contained in:
Eric W. Biederman
parent
ebccffe3d0
commit
ed8c9d7e0d
62 changed files with 1362 additions and 977 deletions
|
|
@ -1,6 +1,7 @@
|
|||
// Needed so the AMD K7 runs correctly.
|
||||
#include <printk.h>
|
||||
#include <cpu/p6/msr.h>
|
||||
#include <cpu/cpufixup.h>
|
||||
|
||||
#define TOP_MEM 0xc001001a
|
||||
#define TOP_MEM2 0xc001001d
|
||||
|
|
@ -10,34 +11,34 @@
|
|||
|
||||
#define MTRRVARDRAMEN (1 << 20)
|
||||
void
|
||||
cpufixup(unsigned long ram_kilobytes)
|
||||
k7_cpufixup(unsigned long ram_kilobytes)
|
||||
{
|
||||
unsigned long lo = 0, hi = 0, i;
|
||||
unsigned long ram_megabytes = ram_kilobytes * 1024;
|
||||
unsigned long lo = 0, hi = 0, i;
|
||||
unsigned long ram_megabytes = ram_kilobytes * 1024;
|
||||
// 8 MB alignment please
|
||||
ram_megabytes += 0x7fffff;
|
||||
ram_megabytes &= (~0x7fffff);
|
||||
// set top_mem registers to ram size
|
||||
printk(KERN_INFO "Setting top_mem to 0x%x\n", ram_megabytes);
|
||||
rdmsr(TOP_MEM, lo, hi);
|
||||
printk(KERN_INFO "TOPMEM was 0x%x:0x$x\n", hi, lo);
|
||||
hi = 0;
|
||||
lo = ram_megabytes;
|
||||
wrmsr(TOP_MEM, lo, hi);
|
||||
// I am setting this even though I won't enable it
|
||||
wrmsr(TOP_MEM2, lo, hi);
|
||||
|
||||
/* zero the IORR's before we enable to prevent
|
||||
* undefined side effects
|
||||
*/
|
||||
lo = hi = 0;
|
||||
for(i = IORR_FIRST; i <= IORR_LAST; i++)
|
||||
wrmsr(i, lo, hi);
|
||||
|
||||
rdmsr(SYSCFG, lo, hi);
|
||||
printk(KERN_INFO "SYSCFG was 0x%x:0x%x\n", hi, lo);
|
||||
lo |= MTRRVARDRAMEN;
|
||||
wrmsr(SYSCFG, lo, hi);
|
||||
rdmsr(SYSCFG, lo, hi);
|
||||
printk(KERN_INFO "SYSCFG IS NOW 0x%x:0x%x\n", hi, lo);
|
||||
ram_megabytes += 0x7fffff;
|
||||
ram_megabytes &= (~0x7fffff);
|
||||
// set top_mem registers to ram size
|
||||
printk_spew("Setting top_mem to 0x%x\n", ram_megabytes);
|
||||
rdmsr(TOP_MEM, lo, hi);
|
||||
printk_spew("TOPMEM was 0x%02x:0x%02x\n", hi, lo);
|
||||
hi = 0;
|
||||
lo = ram_megabytes;
|
||||
wrmsr(TOP_MEM, lo, hi);
|
||||
// I am setting this even though I won't enable it
|
||||
wrmsr(TOP_MEM2, lo, hi);
|
||||
|
||||
/* zero the IORR's before we enable to prevent
|
||||
* undefined side effects
|
||||
*/
|
||||
lo = hi = 0;
|
||||
for(i = IORR_FIRST; i <= IORR_LAST; i++)
|
||||
wrmsr(i, lo, hi);
|
||||
|
||||
rdmsr(SYSCFG, lo, hi);
|
||||
printk_spew("SYSCFG was 0x%x:0x%x\n", hi, lo);
|
||||
lo |= MTRRVARDRAMEN;
|
||||
wrmsr(SYSCFG, lo, hi);
|
||||
rdmsr(SYSCFG, lo, hi);
|
||||
printk_spew("SYSCFG IS NOW 0x%x:0x%x\n", hi, lo);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -12,30 +12,30 @@ static char rcsid[] = "$Id$";
|
|||
#endif
|
||||
|
||||
|
||||
int intel_mtrr_check(void)
|
||||
int mtrr_check(void)
|
||||
{
|
||||
#ifdef i686
|
||||
/* Only Pentium Pro and later have MTRR */
|
||||
unsigned long low, high;
|
||||
|
||||
DBG("\nMTRR check\n");
|
||||
printk_debug("\nMTRR check\n");
|
||||
|
||||
rdmsr(0x2ff, low, high);
|
||||
low = low >> 10;
|
||||
|
||||
DBG("Fixed MTRRs : ");
|
||||
printk_debug("Fixed MTRRs : ");
|
||||
if (low & 0x01)
|
||||
DBG("Enabled\n");
|
||||
printk_debug("Enabled\n");
|
||||
else
|
||||
DBG("Disabled\n");
|
||||
printk_debug("Disabled\n");
|
||||
|
||||
DBG("Variable MTRRs: ");
|
||||
printk_debug("Variable MTRRs: ");
|
||||
if (low & 0x02)
|
||||
DBG("Enabled\n");
|
||||
printk_debug("Enabled\n");
|
||||
else
|
||||
DBG("Disabled\n");
|
||||
printk_debug("Disabled\n");
|
||||
|
||||
DBG("\n");
|
||||
printk_debug("\n");
|
||||
|
||||
post_code(0x93);
|
||||
return ((int) low);
|
||||
|
|
@ -44,46 +44,46 @@ int intel_mtrr_check(void)
|
|||
#endif /* i686 */
|
||||
}
|
||||
|
||||
void intel_display_cpuid(void)
|
||||
void display_cpuid(void)
|
||||
{
|
||||
int op, eax, ebx, ecx, edx;
|
||||
int max_op;
|
||||
|
||||
max_op = 0;
|
||||
|
||||
DBG("\n");
|
||||
printk_debug("\n");
|
||||
|
||||
for (op = 0; op <= max_op; op++) {
|
||||
intel_cpuid(op, &eax, &ebx, &ecx, &edx);
|
||||
cpuid(op, &eax, &ebx, &ecx, &edx);
|
||||
|
||||
if (0 == op) {
|
||||
max_op = eax;
|
||||
DBG("Max cpuid index : %d\n", eax);
|
||||
DBG("Vendor ID : "
|
||||
printk_debug("Max cpuid index : %d\n", eax);
|
||||
printk_debug("Vendor ID : "
|
||||
"%c%c%c%c%c%c%c%c%c%c%c%c\n",
|
||||
ebx, ebx >> 8, ebx >> 16, ebx >> 24, edx,
|
||||
edx >> 8, edx >> 16, edx >> 24, ecx, ecx >> 8,
|
||||
ecx >> 16, ecx >> 24);
|
||||
} else if (1 == op) {
|
||||
DBG("Processor Type : 0x%02x\n",
|
||||
printk_debug("Processor Type : 0x%02x\n",
|
||||
(eax >> 12) & 0x03);
|
||||
DBG("Processor Family : 0x%02x\n",
|
||||
printk_debug("Processor Family : 0x%02x\n",
|
||||
(eax >> 8) & 0x0f);
|
||||
DBG("Processor Model : 0x%02x\n",
|
||||
printk_debug("Processor Model : 0x%02x\n",
|
||||
(eax >> 4) & 0x0f);
|
||||
DBG("Processor Mask : 0x%02x\n",
|
||||
printk_debug("Processor Mask : 0x%02x\n",
|
||||
(ecx >> 0) & 0x0f);
|
||||
DBG("Processor Stepping : 0x%02x\n",
|
||||
printk_debug("Processor Stepping : 0x%02x\n",
|
||||
(eax >> 0) & 0x0f);
|
||||
DBG("Feature flags : 0x%08x\n", edx);
|
||||
printk_debug("Feature flags : 0x%08x\n", edx);
|
||||
} else if (2 == op) {
|
||||
int desc[4];
|
||||
int ii;
|
||||
int _desc;
|
||||
|
||||
DBG("\n");
|
||||
printk_debug("\n");
|
||||
|
||||
DBG("Cache/TLB descriptor values: %d "
|
||||
printk_debug("Cache/TLB descriptor values: %d "
|
||||
"reads required\n", eax & 0xff);
|
||||
|
||||
desc[0] = eax;
|
||||
|
|
@ -93,133 +93,133 @@ void intel_display_cpuid(void)
|
|||
|
||||
for (ii = 1; ii < 16; ii++) {
|
||||
if (desc[ii >> 2] & 0x80000000) {
|
||||
DBG("reserved descriptor\n");
|
||||
printk_debug("reserved descriptor\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
_desc =
|
||||
((desc[ii >> 2]) >> ((ii & 0x3) << 3))
|
||||
& 0xff;
|
||||
DBG("Desc 0x%02x : ", _desc);
|
||||
printk_debug("Desc 0x%02x : ", _desc);
|
||||
|
||||
switch (_desc) {
|
||||
case 0x00:
|
||||
DBG("null\n");
|
||||
printk_debug("null\n");
|
||||
break;
|
||||
|
||||
case 0x01:
|
||||
DBG("Instr TLB: "
|
||||
printk_debug("Instr TLB: "
|
||||
"4KB pages, "
|
||||
"4-way set assoc, "
|
||||
"32 entries\n");
|
||||
break;
|
||||
|
||||
case 0x02:
|
||||
DBG("Instr TLB: "
|
||||
printk_debug("Instr TLB: "
|
||||
"4MB pages, "
|
||||
"fully assoc, " "2 entries\n");
|
||||
break;
|
||||
|
||||
case 0x03:
|
||||
DBG("Data TLB: "
|
||||
printk_debug("Data TLB: "
|
||||
"4KB pages, "
|
||||
"4-way set assoc, "
|
||||
"64 entries\n");
|
||||
break;
|
||||
|
||||
case 0x04:
|
||||
DBG("Data TLB: "
|
||||
printk_debug("Data TLB: "
|
||||
"4MB pages, "
|
||||
"4-way set assoc, "
|
||||
"8 entries\n");
|
||||
break;
|
||||
|
||||
case 0x06:
|
||||
DBG("Inst cache: "
|
||||
printk_debug("Inst cache: "
|
||||
"8K bytes, "
|
||||
"4-way set assoc, "
|
||||
"32 byte line size\n");
|
||||
break;
|
||||
|
||||
case 0x08:
|
||||
DBG("Inst cache: "
|
||||
printk_debug("Inst cache: "
|
||||
"16K bytes, "
|
||||
"4-way set assoc, "
|
||||
"32 byte line size\n");
|
||||
break;
|
||||
|
||||
case 0x0a:
|
||||
DBG("Data cache: "
|
||||
printk_debug("Data cache: "
|
||||
"8K bytes, "
|
||||
"2-way set assoc, "
|
||||
"32 byte line size\n");
|
||||
break;
|
||||
|
||||
case 0x0c:
|
||||
DBG("Data cache: "
|
||||
printk_debug("Data cache: "
|
||||
"16K bytes, "
|
||||
"2-way or 4-way set assoc, "
|
||||
"32 byte line size\n");
|
||||
break;
|
||||
|
||||
case 0x40:
|
||||
DBG("No L2 cache\n");
|
||||
printk_debug("No L2 cache\n");
|
||||
break;
|
||||
|
||||
case 0x41:
|
||||
DBG("L2 Unified cache: "
|
||||
printk_debug("L2 Unified cache: "
|
||||
"128K bytes, "
|
||||
"4-way set assoc, "
|
||||
"32 byte line size\n");
|
||||
break;
|
||||
|
||||
case 0x42:
|
||||
DBG("L2 Unified cache: "
|
||||
printk_debug("L2 Unified cache: "
|
||||
"256K bytes, "
|
||||
"4-way set assoc, "
|
||||
"32 byte line size\n");
|
||||
break;
|
||||
|
||||
case 0x43:
|
||||
DBG("L2 Unified cache: "
|
||||
printk_debug("L2 Unified cache: "
|
||||
"512K bytes, "
|
||||
"4-way set assoc, "
|
||||
"32 byte line size\n");
|
||||
break;
|
||||
|
||||
case 0x44:
|
||||
DBG("L2 Unified cache: "
|
||||
printk_debug("L2 Unified cache: "
|
||||
"1M byte, "
|
||||
"4-way set assoc, "
|
||||
"32 byte line size\n");
|
||||
break;
|
||||
|
||||
case 0x45:
|
||||
DBG("L2 Unified cache: "
|
||||
printk_debug("L2 Unified cache: "
|
||||
"2M byte, "
|
||||
"4-way set assoc, "
|
||||
"32 byte line size\n");
|
||||
break;
|
||||
|
||||
case 0x82:
|
||||
DBG("L2 Unified cache: "
|
||||
printk_debug("L2 Unified cache: "
|
||||
"256K bytes, "
|
||||
"8-way set assoc, "
|
||||
"32 byte line size\n");
|
||||
break;
|
||||
|
||||
default:
|
||||
DBG("UNKNOWN\n");
|
||||
printk_debug("UNKNOWN\n");
|
||||
}
|
||||
}
|
||||
DBG("\n");
|
||||
printk_debug("\n");
|
||||
} else {
|
||||
DBG("op: 0x%02x eax:0x%08x "
|
||||
printk_debug("op: 0x%02x eax:0x%08x "
|
||||
"ebx:0x%08x ecx:0x%08x edx:0x%08x\n",
|
||||
op, eax, ebx, ecx, edx);
|
||||
}
|
||||
}
|
||||
|
||||
DBG("\n");
|
||||
printk_debug("\n");
|
||||
post_code(0x92);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
option i686
|
||||
option INTEL_PPRO_MTRR
|
||||
object microcode.o
|
||||
object mpspec.o
|
||||
object mtrr.o
|
||||
object l2_cache.o
|
||||
object ioapic.o
|
||||
|
|
|
|||
|
|
@ -1,23 +1,27 @@
|
|||
#include <cpu/p6/mtrr.h>
|
||||
|
||||
/* The fixed and variable MTRRs are powered-up with random values, clear them to
|
||||
* MTRR_TYPE_UNCACHABLE for safty reason */
|
||||
* MTRR_TYPE_UNCACHABLE for safty reason
|
||||
*/
|
||||
|
||||
earlymtrr_start:
|
||||
xorl %eax, %eax # clear %eax and %edx
|
||||
xorl %edx, %edx #
|
||||
movl $fixed_mtrr_msr, %esi
|
||||
|
||||
clear_fixed_var_mtrr:
|
||||
lodsw (%esi), %ax
|
||||
testw $0x00, %ax
|
||||
jz set_fixed_mtrr
|
||||
lodsl (%esi), %eax
|
||||
testl %eax, %eax
|
||||
jz clear_fixed_var_mtrr_out
|
||||
|
||||
movzwl %ax, %ecx
|
||||
movl %eax, %ecx
|
||||
xorl %eax, %eax
|
||||
wrmsr
|
||||
|
||||
jmp clear_fixed_var_mtrr
|
||||
clear_fixed_var_mtrr_out:
|
||||
|
||||
#ifdef MEMORY_HOLE
|
||||
set_fixed_mtrr:
|
||||
/* enable Write Back Cache for 0-640KB */
|
||||
movl $MTRRfix64K_00000_MSR, %ecx
|
||||
|
|
@ -31,51 +35,71 @@ set_fixed_mtrr:
|
|||
movl $0x06060606, %edx
|
||||
movl $0x06060606, %eax
|
||||
wrmsr
|
||||
#endif /* MEMORY_HOLE */
|
||||
|
||||
set_var_mtrr:
|
||||
/* enable caching for 0-2(or 4)MB using variable mtrr */
|
||||
mov $0x200, %ecx
|
||||
/* enable caching for 0 - 128MB using variable mtrr */
|
||||
movl $0x200, %ecx
|
||||
rdmsr
|
||||
and $0xfffffff0, %edx
|
||||
or $0x00000000, %edx
|
||||
and $0x00000f00, %eax
|
||||
or $0x00000006, %eax
|
||||
andl $0xfffffff0, %edx
|
||||
orl $0x00000000, %edx
|
||||
andl $0x00000f00, %eax
|
||||
orl $0x00000006, %eax
|
||||
wrmsr
|
||||
|
||||
mov $0x201, %ecx
|
||||
movl $0x201, %ecx
|
||||
rdmsr
|
||||
and $0xfffffff0, %edx
|
||||
or $0x0000000f, %edx
|
||||
and $0x000007ff, %eax
|
||||
or $0xf0000800, %eax
|
||||
andl $0xfffffff0, %edx
|
||||
orl $0x0000000f, %edx
|
||||
andl $0x000007ff, %eax
|
||||
orl $0xf0000800, %eax
|
||||
wrmsr
|
||||
|
||||
#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
|
||||
/* enable write protect caching so we can do execute in place
|
||||
* on the flash rom.
|
||||
*/
|
||||
movl $0x202, %ecx
|
||||
xorl %edx, %edx
|
||||
movl $(XIP_ROM_BASE | 0x005), %eax
|
||||
wrmsr
|
||||
|
||||
movl $0x203, %ecx
|
||||
movl $0x0000000f, %edx
|
||||
movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
|
||||
wrmsr
|
||||
#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
|
||||
|
||||
enable_mtrr:
|
||||
/* Set the default memory type and enable fixed and variable MTRRs */
|
||||
movl $0x2ff, %ecx
|
||||
rdmsr
|
||||
and $0xfffff300, %eax
|
||||
xorl %edx, %edx
|
||||
#ifdef MEMORY_HOLE
|
||||
/* Enable Fixed and Variable MTRRs */
|
||||
or $0x00000c00, %eax
|
||||
movl $0x00000c00, %eax
|
||||
#else
|
||||
/* Enable Variable MTRRs */
|
||||
movl $0x00000800, %eax
|
||||
#endif /* MEMORY_HOLE */
|
||||
wrmsr
|
||||
|
||||
/* enable cache */
|
||||
mov %cr0, %eax
|
||||
and $0x9fffffff,%eax
|
||||
mov %eax, %cr0
|
||||
movl %cr0, %eax
|
||||
andl $0x9fffffff,%eax
|
||||
movl %eax, %cr0
|
||||
|
||||
jmp earlymtrr_end
|
||||
|
||||
fixed_mtrr_msr:
|
||||
.word 0x250, 0x258, 0x259
|
||||
.word 0x268, 0x269, 0x26A
|
||||
.word 0x26B, 0x26C, 0x26D
|
||||
.word 0x26E, 0x26F
|
||||
.long 0x250, 0x258, 0x259
|
||||
.long 0x268, 0x269, 0x26A
|
||||
.long 0x26B, 0x26C, 0x26D
|
||||
.long 0x26E, 0x26F
|
||||
var_mtrr_msr:
|
||||
.word 0x200, 0x201, 0x202, 0x203
|
||||
.word 0x204, 0x205, 0x206, 0x207
|
||||
.word 0x208, 0x209, 0x20A, 0x20B
|
||||
.word 0x20C, 0x20D, 0x20E, 0x20F
|
||||
.word 0x000 /* NULL, end of table */
|
||||
.long 0x200, 0x201, 0x202, 0x203
|
||||
.long 0x204, 0x205, 0x206, 0x207
|
||||
.long 0x208, 0x209, 0x20A, 0x20B
|
||||
.long 0x20C, 0x20D, 0x20E, 0x20F
|
||||
.long 0x000 /* NULL, end of table */
|
||||
|
||||
earlymtrr_end:
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ void cache_disable(void)
|
|||
unsigned int tmp;
|
||||
|
||||
/* Disable cache */
|
||||
DBG("Disable Cache\n");
|
||||
printk_debug("Disable Cache\n");
|
||||
|
||||
/* Write back the cache and flush TLB */
|
||||
asm volatile ("movl %%cr0, %0\n\t"
|
||||
|
|
@ -81,37 +81,39 @@ void cache_enable(void)
|
|||
"movl %0, %%cr0\n\t"
|
||||
:"=r" (tmp) : : "memory");
|
||||
|
||||
DBG("Enable Cache\n");
|
||||
printk_debug("Enable Cache\n");
|
||||
}
|
||||
|
||||
// GOTO bad and GOTO done added by rgm.
|
||||
// there were too many ways that you could leave this thing with the
|
||||
// cache turned off!
|
||||
// TODO: save whether it was on or not, and restore that state on exit.
|
||||
int intel_l2_configure()
|
||||
int p6_configure_l2_cache()
|
||||
{
|
||||
unsigned int eax, ebx, ecx, edx;
|
||||
int signature, tmp;
|
||||
int cache_size;
|
||||
int result;
|
||||
|
||||
intel_cpuid(0, &eax, &ebx, &ecx, &edx);
|
||||
printk_info("Configuring L2 cache...");
|
||||
cpuid(0, &eax, &ebx, &ecx, &edx);
|
||||
|
||||
if (ebx != 0x756e6547 || edx != 0x49656e69 || ecx != 0x6c65746e) {
|
||||
printk(KERN_ERR "Not 'GenuineIntel' Processor\n");
|
||||
printk_err( "Not 'GenuineIntel' Processor\n");
|
||||
goto bad;
|
||||
}
|
||||
|
||||
intel_cpuid(1, &eax, &ebx, &ecx, &edx);
|
||||
cpuid(1, &eax, &ebx, &ecx, &edx);
|
||||
|
||||
/* Mask out the stepping */
|
||||
signature = eax & 0xfff0;
|
||||
if (signature & 0x1000) {
|
||||
DBG("Overdrive chip no L2 cache configuration\n");
|
||||
printk_debug("Overdrive chip no L2 cache configuration\n");
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (signature < 0x630 || signature >= 0x680) {
|
||||
DBG("CPU signature of %x so no L2 cache configuration\n",
|
||||
printk_debug("CPU signature of %x so no L2 cache configuration\n",
|
||||
signature);
|
||||
goto done;
|
||||
}
|
||||
|
|
@ -120,7 +122,7 @@ int intel_l2_configure()
|
|||
rdmsr(BBL_CR_CTL3, eax, edx);
|
||||
/* If bit 23 (L2 Hardware disable) is set then done */
|
||||
if (eax & 0x800000) {
|
||||
DBG("L2 Hardware disabled\n");
|
||||
printk_debug("L2 Hardware disabled\n");
|
||||
goto done;
|
||||
}
|
||||
|
||||
|
|
@ -133,7 +135,7 @@ int intel_l2_configure()
|
|||
/* Mask out [22-24] Clock frequency ratio */
|
||||
eax &= 0x1c00000;
|
||||
if (eax == 0xc00000 || eax == 0x1000000) {
|
||||
printk(KERN_ERR "Incorrect clock frequency ratio %x\n",
|
||||
printk_err( "Incorrect clock frequency ratio %x\n",
|
||||
eax);
|
||||
goto bad;
|
||||
}
|
||||
|
|
@ -173,7 +175,7 @@ int intel_l2_configure()
|
|||
/* Mask out [22-24] Clock frequency ratio */
|
||||
eax &= 0x3c00000;
|
||||
if (eax == 0xc00000 || eax == 0x3000000) {
|
||||
printk(KERN_ERR "Incorrect clock frequency ratio %x\n",
|
||||
printk_err( "Incorrect clock frequency ratio %x\n",
|
||||
eax);
|
||||
goto bad;
|
||||
}
|
||||
|
|
@ -220,7 +222,7 @@ int intel_l2_configure()
|
|||
/* Shift to [1:0] */
|
||||
v >>= 26;
|
||||
|
||||
DBG("Sending %x to set_l2_register4\n", v);
|
||||
printk_debug("Sending %x to set_l2_register4\n", v);
|
||||
if (set_l2_register4(v) != 0)
|
||||
goto bad;
|
||||
|
||||
|
|
@ -231,7 +233,7 @@ int intel_l2_configure()
|
|||
/* Read L2 register 0 */
|
||||
tmp = read_l2(0);
|
||||
if (tmp < 0) {
|
||||
printk(KERN_ERR "Failed to read_l2(0)\n");
|
||||
printk_err("Failed to read_l2(0)\n");
|
||||
goto bad;
|
||||
}
|
||||
|
||||
|
|
@ -246,18 +248,18 @@ int intel_l2_configure()
|
|||
}
|
||||
|
||||
if (calculate_l2_ecc() != 0) {
|
||||
printk(KERN_ERR "Failed to calculate L2 ECC\n");
|
||||
printk_err( "Failed to calculate L2 ECC\n");
|
||||
goto bad;
|
||||
}
|
||||
|
||||
if (calculate_l2_physical_address_range() != 0) {
|
||||
printk(KERN_ERR
|
||||
printk_err(
|
||||
"Failed to calculate L2 physical address range\n");
|
||||
goto bad;
|
||||
}
|
||||
|
||||
if (calculate_l2_cache_size() != 0) {
|
||||
printk(KERN_ERR "Failed to calculate L2 cache size\n");
|
||||
printk_err("Failed to calculate L2 cache size\n");
|
||||
goto bad;
|
||||
}
|
||||
|
||||
|
|
@ -272,7 +274,7 @@ int intel_l2_configure()
|
|||
cache_size = cache_size << 3;
|
||||
|
||||
/* Cache is 4 way for each address */
|
||||
DBG("L2 Cache size is %dK\n", cache_size * 4 / 1024);
|
||||
printk_debug("L2 Cache size is %dK\n", cache_size * 4 / 1024);
|
||||
|
||||
/* Write to all cache lines to initialize */
|
||||
while (cache_size > 0) {
|
||||
|
|
@ -287,14 +289,14 @@ int intel_l2_configure()
|
|||
* MESI = Invalid
|
||||
*/
|
||||
if (signal_l2(0, cache_size, 0, 0, way, 0x1c) != 0) {
|
||||
printk(KERN_ERR
|
||||
printk_err(
|
||||
"Failed on signal_l2(%x, %x)\n",
|
||||
cache_size, way);
|
||||
goto bad;
|
||||
}
|
||||
}
|
||||
}
|
||||
DBG("L2 Cache lines initialized\n");
|
||||
printk_debug("L2 Cache lines initialized\n");
|
||||
|
||||
/* Disable cache */
|
||||
cache_disable();
|
||||
|
|
@ -309,7 +311,7 @@ int intel_l2_configure()
|
|||
|
||||
/* Write 0 to L2 control register 5 */
|
||||
if (write_l2(5, 0) != 0) {
|
||||
printk(KERN_ERR "write_l2(5, 0) failed\n");
|
||||
printk_err("write_l2(5, 0) failed\n");
|
||||
goto done;
|
||||
}
|
||||
|
||||
|
|
@ -333,13 +335,15 @@ int intel_l2_configure()
|
|||
|
||||
/* Turn on cache. Both L1 and L2 are now active. Wahoo! */
|
||||
done:
|
||||
result = 0;
|
||||
out:
|
||||
cache_enable();
|
||||
|
||||
return 0;
|
||||
printk_info("done.\n");
|
||||
return result;
|
||||
bad:
|
||||
// it was probably on when we got here, so turn it back on.
|
||||
cache_enable();
|
||||
return -1;
|
||||
result = -1;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Setup address_high:address_low, data_high:data_low into the L2
|
||||
|
|
@ -536,7 +540,7 @@ static int calculate_l2_latency(void)
|
|||
/* Read an undocumented MSR */
|
||||
rdmsr(0x17, eax, edx);
|
||||
|
||||
DBG("rdmsr(0x17) = %x, %x\n", eax, edx);
|
||||
printk_debug("rdmsr(0x17) = %x, %x\n", eax, edx);
|
||||
|
||||
/* Mask out [23:20] in EDX. Are Intel trying to hide this?? */
|
||||
edx &= 0x1e00000;
|
||||
|
|
@ -565,12 +569,12 @@ static int calculate_l2_latency(void)
|
|||
else
|
||||
return -1;
|
||||
|
||||
intel_cpuid(1, &eax, &ebx, &ecx, &edx);
|
||||
cpuid(1, &eax, &ebx, &ecx, &edx);
|
||||
|
||||
/* Mask out Model/Type */
|
||||
eax &= 0xfff0;
|
||||
|
||||
DBG("L2 latency type = %x\n", t);
|
||||
printk_debug("L2 latency type = %x\n", t);
|
||||
|
||||
if (eax == 0x650) {
|
||||
/* Read EBL_CR_POWERON */
|
||||
|
|
@ -597,13 +601,13 @@ static int calculate_l2_latency(void)
|
|||
} else
|
||||
return -1;
|
||||
|
||||
DBG("Searching for key %x\n", eax);
|
||||
printk_debug("Searching for key %x\n", eax);
|
||||
|
||||
/* Search table for matching entry */
|
||||
for (le = latency_table; le->key != eax; le++) {
|
||||
/* Fail if we get to the end of the table */
|
||||
if (le->key == 0xff) {
|
||||
printk(KERN_ERR
|
||||
printk_err(
|
||||
"Could not find key %x in latency table\n",
|
||||
eax);
|
||||
return -1;
|
||||
|
|
@ -613,7 +617,7 @@ static int calculate_l2_latency(void)
|
|||
l = le->value;
|
||||
}
|
||||
|
||||
DBG("L2 Cache latency is %d\n", l / 2);
|
||||
printk_debug("L2 Cache latency is %d\n", l / 2);
|
||||
|
||||
/* Read BBL_CR_CTL3 */
|
||||
rdmsr(0x11e, eax, edx);
|
||||
|
|
@ -709,7 +713,7 @@ static int calculate_l2_cache_size(void)
|
|||
/* Write new value into BBL_CR_CTL3 */
|
||||
wrmsr(0x11e, eax, edx);
|
||||
|
||||
DBG("Maximum cache mask is %x\n", cache_setting);
|
||||
printk_debug("Maximum cache mask is %x\n", cache_setting);
|
||||
|
||||
/* Write aaaaaaaa:aaaaaaaa to address 0 in the l2 cache */
|
||||
v = test_l2_address_alias(0, 0, 0xaaaaaaaa, 0xaaaaaaaa);
|
||||
|
|
@ -753,14 +757,14 @@ static int calculate_l2_cache_size(void)
|
|||
/* Write cache size into BBL_CR_CTL3 */
|
||||
wrmsr(0x11e, eax, edx);
|
||||
|
||||
DBG("L2 Cache Mask is %x\n", size);
|
||||
printk_debug("L2 Cache Mask is %x\n", size);
|
||||
|
||||
/* Shift to [6:2] */
|
||||
size >>= 11;
|
||||
|
||||
v = read_l2(2);
|
||||
|
||||
DBG("read_l2(2) = %x\n", v);
|
||||
printk_debug("read_l2(2) = %x\n", v);
|
||||
|
||||
if (v < 0)
|
||||
return -1;
|
||||
|
|
@ -773,7 +777,7 @@ static int calculate_l2_cache_size(void)
|
|||
/* Or in this size */
|
||||
v |= size;
|
||||
|
||||
DBG("write_l2(2) = %x\n", v);
|
||||
printk_debug("write_l2(2) = %x\n", v);
|
||||
|
||||
if (write_l2(2, v) != 0)
|
||||
return -1;
|
||||
|
|
@ -782,7 +786,7 @@ static int calculate_l2_cache_size(void)
|
|||
|
||||
a = read_l2(2);
|
||||
|
||||
DBG("read_l2(2) = %x\n", a);
|
||||
printk_debug("read_l2(2) = %x\n", a);
|
||||
|
||||
if (a < 0)
|
||||
return -1;
|
||||
|
|
@ -794,7 +798,7 @@ static int calculate_l2_cache_size(void)
|
|||
|
||||
a &= 0xf;
|
||||
|
||||
DBG("Calculated a = %x\n", a);
|
||||
printk_debug("Calculated a = %x\n", a);
|
||||
|
||||
if (a == 0)
|
||||
return -1;
|
||||
|
|
@ -836,7 +840,7 @@ static int calculate_l2_physical_address_range(void)
|
|||
else
|
||||
r3 &= 0x7;
|
||||
|
||||
DBG("L2 Physical Address Range is %dM\n", (1 << r3) * 512);
|
||||
printk_debug("L2 Physical Address Range is %dM\n", (1 << r3) * 512);
|
||||
|
||||
/* Shift into [22:20] */
|
||||
r3 = r3 << 20;
|
||||
|
|
@ -877,7 +881,7 @@ static int calculate_l2_ecc(void)
|
|||
rdmsr(0x118, eax, edx);
|
||||
|
||||
if (eax == data1) {
|
||||
DBG("L2 ECC Checking is enabled\n");
|
||||
printk_debug("L2 ECC Checking is enabled\n");
|
||||
|
||||
/* Set ECC Check Enable in BBL_CR_CTL3 */
|
||||
rdmsr(0x11e, eax, edx);
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@ static char rcsid[] = "$Id$";
|
|||
#include <cpu/p6/msr.h>
|
||||
#include <printk.h>
|
||||
#include <cpu/p5/cpuid.h>
|
||||
#include <cpu/cpufixup.h>
|
||||
|
||||
struct microcode {
|
||||
unsigned int hdrver;
|
||||
|
|
@ -299,7 +300,7 @@ unsigned int microcode_updates [] = {
|
|||
0x57688086, 0x218e4005, 0xca054e3d, 0xc1a3c3ec,
|
||||
};
|
||||
|
||||
void intel_display_cpuid_microcode(void)
|
||||
static void display_cpuid_update_microcode(void)
|
||||
{
|
||||
unsigned int eax, ebx, ecx, edx;
|
||||
unsigned int pf, rev, sig, val[2];
|
||||
|
|
@ -308,7 +309,7 @@ void intel_display_cpuid_microcode(void)
|
|||
|
||||
/* cpuid sets msr 0x8B iff a microcode update has been loaded. */
|
||||
wrmsr(0x8B, 0, 0);
|
||||
intel_cpuid(1, &eax, &ebx, &ecx, &edx);
|
||||
cpuid(1, &eax, &ebx, &ecx, &edx);
|
||||
rdmsr(0x8B, val[0], rev);
|
||||
x86_model = (eax >>4) & 0x0f;
|
||||
sig = eax;
|
||||
|
|
@ -318,7 +319,7 @@ void intel_display_cpuid_microcode(void)
|
|||
rdmsr(0x17, val[0], val[1]);
|
||||
pf = 1 << ((val[1] >> 18) & 7);
|
||||
}
|
||||
printk(KERN_INFO "microcode_info: sig = 0x%08x pf=0x%08x rev = 0x%08x\n",
|
||||
printk_info("microcode_info: sig = 0x%08x pf=0x%08x rev = 0x%08x\n",
|
||||
sig, pf, rev);
|
||||
|
||||
m = (void *)µcode_updates;
|
||||
|
|
@ -327,8 +328,14 @@ void intel_display_cpuid_microcode(void)
|
|||
wrmsr(0x79, (unsigned int)&m[i].bits, 0);
|
||||
__asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx");
|
||||
rdmsr(0x8B, val[0], val[1]);
|
||||
printk(KERN_INFO "microcode updated from revision %d to %d\n",
|
||||
printk_info("microcode updated from revision %d to %d\n",
|
||||
rev, val[1]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void p6_cpufixup(unsigned long totalram)
|
||||
{
|
||||
printk_info("Updating microcode\n");
|
||||
display_cpuid_update_microcode();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@ static char rcsid[] = "$Id$";
|
|||
|
||||
#include <cpu/p6/msr.h>
|
||||
#include <cpu/p6/mtrr.h>
|
||||
#include <cpu/k7/mtrr.h>
|
||||
#include <printk.h>
|
||||
#include <subr.h>
|
||||
|
||||
|
|
@ -44,58 +45,76 @@ static unsigned int mtrr_msr[] = {
|
|||
|
||||
#ifndef HAVE_MTRR_TABLE
|
||||
|
||||
/* We want to cache memory as efficiently as possible.
|
||||
*/
|
||||
#define MTRR_TYPE_RAM MTRR_TYPE_WRBACK
|
||||
/* We can't use Write Combining on a legacy frame buffer because
|
||||
* it is incompatible with EGA 16 color video modes...
|
||||
*/
|
||||
#define MTRR_TYPE_FB MTRR_TYPE_UNCACHABLE
|
||||
/* For areas that are supposed to cover roms it makes no
|
||||
* sense to cache writes.
|
||||
*/
|
||||
#define MTRR_TYPE_ROM MTRR_TYPE_WRPROT
|
||||
|
||||
|
||||
#ifdef MEMORY_HOLE
|
||||
#define RAM MTRR_TYPE_RAM
|
||||
#define FB MTRR_TYPE_FB
|
||||
#define ROM MTRR_TYPE_ROM
|
||||
#else
|
||||
#define RAM MTRR_TYPE_RAM
|
||||
#define FB MTRR_TYPE_RAM
|
||||
#define ROM MTRR_TYPE_RAM
|
||||
#endif /* MEMORY_HOLE */
|
||||
|
||||
static unsigned char fixed_mtrr_values[][4] = {
|
||||
/* MTRRfix64K_00000_MSR, defines memory range from 0KB to 512 KB, each byte cover 64KB area */
|
||||
{MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK},
|
||||
{MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK},
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
|
||||
/* MTRRfix16K_80000_MSR, defines memory range from 512KB to 640KB, each byte cover 16KB area */
|
||||
{MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK},
|
||||
{MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK},
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
|
||||
/* MTRRfix16K_A0000_MSR, defines memory range from A0000 to C0000, each byte cover 16KB area */
|
||||
{MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB},
|
||||
{MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB},
|
||||
{FB, FB, FB, FB}, {FB, FB, FB, FB},
|
||||
|
||||
/* MTRRfix4K_C0000_MSR, defines memory range from C0000 to C8000, each byte cover 4KB area */
|
||||
{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
|
||||
{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
|
||||
{ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM},
|
||||
|
||||
/* MTRRfix4K_C8000_MSR, defines memory range from C8000 to D0000, each byte cover 4KB area */
|
||||
{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
|
||||
{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
|
||||
{ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM},
|
||||
|
||||
/* MTRRfix4K_D0000_MSR, defines memory range from D0000 to D8000, each byte cover 4KB area */
|
||||
{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
|
||||
{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
|
||||
{ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM},
|
||||
|
||||
/* MTRRfix4K_D8000_MSR, defines memory range from D8000 to E0000, each byte cover 4KB area */
|
||||
{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
|
||||
{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
|
||||
{ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM},
|
||||
|
||||
/* MTRRfix4K_E0000_MSR, defines memory range from E0000 to E8000, each byte cover 4KB area */
|
||||
{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
|
||||
{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
|
||||
{ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM},
|
||||
|
||||
/* MTRRfix4K_E8000_MSR, defines memory range from E8000 to F0000, each byte cover 4KB area */
|
||||
{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
|
||||
{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
|
||||
{ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM},
|
||||
|
||||
/* MTRRfix4K_F0000_MSR, defines memory range from F0000 to F8000, each byte cover 4KB area */
|
||||
{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
|
||||
{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
|
||||
{ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM},
|
||||
|
||||
/* MTRRfix4K_F8000_MSR, defines memory range from F8000 to 100000, each byte cover 4KB area */
|
||||
{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
|
||||
{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
|
||||
{ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM},
|
||||
};
|
||||
|
||||
#undef FB
|
||||
#undef RAM
|
||||
#undef ROM
|
||||
#undef MTRR_TYPE_RAM
|
||||
#undef MTRR_TYPE_FB
|
||||
#undef MTRR_TYPE_ROM
|
||||
|
||||
#else
|
||||
extern unsigned char fixed_mtrr_values[][4];
|
||||
#endif
|
||||
|
||||
void
|
||||
intel_enable_fixed_mtrr()
|
||||
static void intel_enable_fixed_mtrr(void)
|
||||
{
|
||||
unsigned long low, high;
|
||||
|
||||
|
|
@ -104,8 +123,7 @@ intel_enable_fixed_mtrr()
|
|||
wrmsr(MTRRdefType_MSR, low, high);
|
||||
}
|
||||
|
||||
void
|
||||
intel_enable_var_mtrr()
|
||||
static void intel_enable_var_mtrr(void)
|
||||
{
|
||||
unsigned long low, high;
|
||||
|
||||
|
|
@ -116,7 +134,7 @@ intel_enable_var_mtrr()
|
|||
|
||||
/* setting fixed mtrr, you can do some experiments with different memory type
|
||||
defined in the table "fixed_mtrr_values" */
|
||||
void intel_set_fixed_mtrr()
|
||||
static void intel_set_fixed_mtrr(void)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned long low, high;
|
||||
|
|
@ -129,7 +147,7 @@ void intel_set_fixed_mtrr()
|
|||
}
|
||||
|
||||
/* setting variable mtrr, comes from linux kernel source */
|
||||
void intel_set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size, unsigned char type)
|
||||
static void intel_set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size, unsigned char type)
|
||||
{
|
||||
unsigned int tmp;
|
||||
|
||||
|
|
@ -197,28 +215,36 @@ static __inline__ unsigned int fms(unsigned int x)
|
|||
* ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB)
|
||||
*/
|
||||
#ifdef INTEL_PPRO_MTRR
|
||||
#ifdef ENABLE_FIXED_AND_VARIABLE_MTRRS
|
||||
void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK)
|
||||
|
||||
/* 2 MTRRS are reserved for the operating system */
|
||||
#define BIOS_MTRRS 6
|
||||
#define OS_MTRRS 2
|
||||
#define MTRRS (BIOS_MTRRS + OS_MTRRS)
|
||||
|
||||
void setup_mtrrs(unsigned long ramsizeK)
|
||||
{
|
||||
unsigned int reg = 0;
|
||||
unsigned long range_wb, range_uc;
|
||||
unsigned long rambase;
|
||||
unsigned long romendK;
|
||||
|
||||
DBG("\n");
|
||||
printk_debug("\n");
|
||||
rambase = 0;
|
||||
|
||||
while (ramsizeK != 0 && reg <= 6) {
|
||||
while (ramsizeK != 0 && reg < BIOS_MTRRS) {
|
||||
post_code(0x60 + reg);
|
||||
|
||||
range_wb = 1 << (fms(ramsizeK - 1) + 1);
|
||||
range_uc = range_wb - ramsizeK;
|
||||
|
||||
if ((range_uc == 0) || ((ramsizeK % range_uc) == 0)) {
|
||||
DBG("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type: WB\n",
|
||||
printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type: WB\n",
|
||||
reg, rambase >> 10, range_wb >> 10);
|
||||
intel_set_var_mtrr(reg++, rambase * 1024, range_wb * 1024,
|
||||
MTRR_TYPE_WRBACK);
|
||||
rambase += ramsizeK;
|
||||
|
||||
DBG("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type: UC\n",
|
||||
printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type: UC\n",
|
||||
reg, rambase >> 10, range_uc >> 10);
|
||||
intel_set_var_mtrr(reg++, rambase * 1024, range_uc * 1024,
|
||||
MTRR_TYPE_UNCACHABLE);
|
||||
|
|
@ -226,7 +252,7 @@ void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK)
|
|||
} else {
|
||||
range_wb >>= 1;
|
||||
|
||||
DBG("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type: WB\n",
|
||||
printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type: WB\n",
|
||||
reg, rambase >> 10, range_wb >> 10);
|
||||
intel_set_var_mtrr(reg++, rambase * 1024, range_wb * 1024,
|
||||
MTRR_TYPE_WRBACK);
|
||||
|
|
@ -235,19 +261,34 @@ void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK)
|
|||
ramsizeK -= range_wb;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
|
||||
#if XIP_ROM_SIZE < 4096
|
||||
#error XIP_ROM_SIZE must be at least 4K
|
||||
#endif
|
||||
#if XIP_ROM_SIZE & (XIP_ROM_SIZE -1)
|
||||
#error XIP_ROM_SIZE must be a power of two
|
||||
#endif
|
||||
#if XIP_ROM_BASE & (XIP_ROM_SIZE -1)
|
||||
#error XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
|
||||
#endif
|
||||
/* I assume that XIP_ROM_SIZE is a power of two
|
||||
* and that XIP_ROM_BASE is power of tow aligned.
|
||||
*/
|
||||
romendK = (XIP_ROM_BASE + XIP_ROM_SIZE) >>10;
|
||||
if ((reg < BIOS_MTRRS) &&
|
||||
((XIP_ROM_BASE > rambase) || (romendK > rambase))) {
|
||||
intel_set_var_mtrr(reg++, XIP_ROM_BASE, XIP_ROM_SIZE,
|
||||
MTRR_TYPE_WRPROT);
|
||||
}
|
||||
#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
|
||||
/* Clear out the extra MTRR's */
|
||||
while(reg < MTRRS) {
|
||||
intel_set_var_mtrr(reg++, 0, 0, 0);
|
||||
}
|
||||
intel_set_fixed_mtrr();
|
||||
|
||||
/* enable fixed MTRR */
|
||||
intel_enable_fixed_mtrr();
|
||||
intel_enable_var_mtrr();
|
||||
}
|
||||
#else /* ENABLE_FIXED_AND_VARIABLE_MTRRS */
|
||||
void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK)
|
||||
{
|
||||
DBG("\n");
|
||||
intel_set_var_mtrr(0, 0, ramsizeK * 1024, MTRR_TYPE_WRBACK);
|
||||
intel_enable_var_mtrr();
|
||||
}
|
||||
#endif /* ENABLE_FIXED_AND_VARIABLE_MTRRS */
|
||||
#endif /* INTEL_PPRO_MTRR */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue