diff --git a/src/arch/alpha/lib/hardwaremain.c b/src/arch/alpha/lib/hardwaremain.c index aaf634911f..d4f8af19cd 100644 --- a/src/arch/alpha/lib/hardwaremain.c +++ b/src/arch/alpha/lib/hardwaremain.c @@ -9,10 +9,10 @@ void hardwaremain(unsigned long signature, unsigned long memsize, early_mainboard_init(); displayinit(); - printk("\n\nsignature=0x%016lx memsize=0x%016lx cpu_speed=0x%016lx\n", + printk_info("\n\nsignature=0x%016lx memsize=0x%016lx cpu_speed=0x%016lx\n", signature, memsize, cpu_speed); elfboot(memsize >> 10 /* In kilobytes */); - printk("\n after elfboot\n"); + printk_err("\n after elfboot\n"); } void fatal_error(unsigned long exception_handler, unsigned long exception_at, @@ -21,9 +21,9 @@ void fatal_error(unsigned long exception_handler, unsigned long exception_at, /* Just in case we are totally messed up */ early_mainboard_init(); displayinit(); - printk("\n\nFault: 0x%0lx\n", exception_handler); - printk("PC: 0x%0lx\n", exception_at); - printk("RA: 0x%0lx\n", return_address); + printk_emerg("\n\nFault: 0x%0lx\n", exception_handler); + printk_emerg("PC: 0x%0lx\n", exception_at); + printk_emerg("RA: 0x%0lx\n", return_address); /* Now spin forever */ while(1) {;} } diff --git a/src/arch/i386/lib/Config b/src/arch/i386/lib/Config index 9c1b74211b..7a8a030079 100644 --- a/src/arch/i386/lib/Config +++ b/src/arch/i386/lib/Config @@ -1,3 +1,4 @@ object i386_subr.o object params.o object hardwaremain.o +object pirq_routing.o diff --git a/src/arch/i386/lib/hardwaremain.c b/src/arch/i386/lib/hardwaremain.c index 0396444107..806ebd723a 100644 --- a/src/arch/i386/lib/hardwaremain.c +++ b/src/arch/i386/lib/hardwaremain.c @@ -32,57 +32,122 @@ it with the version available from LANL. static char rcsid[] = "$Id$"; #endif -#include -#include +#include +#include #include #include -#include -#include #include #include - -void intel_main() -{ - // These are only used here, so don't bother putting them in a .h - void mainboard_fixup(void); - void nvram_on(void); - void keyboard_on(void); - void framebuffer_on(void); - void intel_copy_irq_routing_table(void); - unsigned long sizeram(void); - void intel_cache_on(unsigned long base, unsigned long totalram); - void intel_zero_irq_settings(void); - void intel_check_irq_routing_table(void); - void intel_interrupts_on(); - -#ifdef FINAL_MAINBOARD_FIXUP - void final_mainboard_fixup(void); -#endif /* FINAL_MAINBOARD_FIXUP */ -#ifdef USE_NEW_SUPERIO_INTERFACE - extern struct superio *all_superio; - extern int nsuperio; - extern void handle_superio(int pass, struct superio *s, int nsuperio); +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(SMP) +#include +#include #endif -#ifdef CONFIGURE_L2_CACHE - int intel_l2_configure(); -#endif /* CONFIGURE_L2_CACHE */ -#ifdef CPU_FIXUP - // some cpus need a fixup done. This is the hook for doing that - // For now we call it after pci config and sizing. - // we may move it earlier for speed. + +static int cpu_initialize(unsigned long totalram) +{ + /* Because we busy wait at the printk spinlock. + * It is important to keep the number of printed messages + * from secondary cpus to a minimum, when debugging is + * disabled. + */ + int processor_id = this_processors_id(); + printk_notice("Initializing CPU #%d\n", processor_id); + + /* some cpus need a fixup done. This is the hook for doing that. */ + cpufixup(totalram); + + /* Turn on caching if we haven't already */ + cache_on(totalram); + + display_cpuid(); + mtrr_check(); + + /* now that everything is really up, enable the l2 cache if desired. + * The enable can wait until this point, because linuxbios and it's + * data areas are tiny, easily fitting into the L1 cache. + */ + configure_l2_cache(); + interrupts_on(); + printk_info("CPU #%d Initialized\n", processor_id); + return processor_id; +} + +static unsigned long get_ramsize(void) +{ + unsigned long totalram; + totalram = sizeram(); + // can't size just yet ... + // mainboard totalram sizing may not be up yet. If it is not ready, + // take a default of 64M + if (!totalram) + totalram = 64 * 1024; + return totalram; +} + +#ifdef SMP +/* Number of cpus that are currently running in linuxbios */ +static atomic_t active_cpus = ATOMIC_INIT(1); + +void secondary_cpu_init(void) +{ + unsigned long totalram; + int processor_id; + + atomic_inc(&active_cpus); + totalram = get_ramsize(); + processor_id = cpu_initialize(totalram); + atomic_dec(&active_cpus); + stop_cpu(processor_id); +} + +static void wait_for_other_cpus(void) +{ + int old_active_count, active_count; + old_active_count = 1; + active_count = atomic_read(&active_cpus); + while(active_count > 1) { + if (active_count != old_active_count) { + printk_info("Waiting for %d CPUS to stop\n", active_count); + old_active_count = active_count; + } + active_count = atomic_read(&active_cpus); + } +} +#else /* SMP */ +#define wait_for_other_cpus() do {} while(0) +#endif /* SMP */ + +void hardwaremain(int boot_complete) +{ // Comment: the NEW_SUPERIO architecture is actually pretty good. // I think we need to move to the same sort of architecture for // everything: A config file generated sequence of calls // for initializing all the chips. We stick with this // for now -- rgm. - void cpufixup(unsigned long totalram); +#ifdef USE_NEW_SUPERIO_INTERFACE + extern struct superio *all_superio; + extern int nsuperio; + extern void handle_superio(int pass, struct superio *s, int nsuperio); #endif - -#ifdef UPDATE_MICROCODE - void intel_display_cpuid_microcode(void); -#endif /* UPDATE_MICROCODE */ - /* the order here is a bit tricky. We don't want to do much of * anything that uses config registers until after PciAllocateResources * since that function also figures out what kind of config strategy @@ -99,138 +164,102 @@ void intel_main() post_code(0x39); - printk(KERN_INFO "Reached intel_main().\n"); + printk_notice("LinuxBIOS %s...\n", (boot_complete)?"rebooting":"booting"); post_code(0x40); -#ifdef UPDATE_MICROCODE - post_code(0x41); - printk(KERN_INFO "Updating microcode\n"); - intel_display_cpuid_microcode(); -#endif /* UPDATE_MICROCODE */ - post_code(0x42); + /* If we have already booted attempt a hard reboot */ + if (boot_complete) { + hard_reset(); + } // pick how to scan the bus. This is first so we can get at memory size. - printk(KERN_INFO "Finding PCI confiuration type...\n"); + printk_info("Finding PCI configuration type.\n"); pci_set_method(); post_code(0x5f); #ifdef USE_NEW_SUPERIO_INTERFACE handle_superio(0, all_superio, nsuperio); #endif - printk(KERN_INFO "Scanning PCI bus..."); pci_enumerate(); post_code(0x66); - printk(KERN_INFO "done\n"); // The framebuffer can change how much memory you have. // So you really need to run this before you size ram. -#ifdef HAVE_FRAMEBUFFER framebuffer_on(); -#endif /* HAVE_FRAMEBUFFER */ - totalram = sizeram(); + totalram = get_ramsize(); post_code(0x70); - printk(KERN_INFO "totalram: %ldM\n", totalram/1024); + printk_info("totalram: %ldM\n", totalram/1024); - // can't size just yet ... - // mainboard totalram sizing may not be up yet. If it is not ready, - // take a default of 64M - if (!totalram) - totalram = 64 * 1024; + /* Fully initialize the cpu before configuring the bus */ + cpu_initialize(totalram); -#ifdef CPU_FIXUP - // cpu-dependent fixup. - cpufixup(totalram); -#endif - // Turn on cache before configuring the bus. - printk(KERN_INFO "Enabling cache..."); - intel_cache_on(0, totalram); - post_code(0x80); - printk(KERN_INFO "done.\n"); + /* Now start the other cpus initializing + * The sooner they start the sooner they stop. + */ + startup_other_cpus(); - printk(KERN_INFO "Allocating PCI resources..."); // Now do the real bus // we round the total ram up a lot for thing like the SISFB, which // shares high memory with the CPU. pci_configure(); post_code(0x88); + pci_enable(); post_code(0x90); - printk(KERN_INFO "done.\n"); - -#ifdef IOAPIC - /* set up the IO-APIC for the clock interrupt. */ - post_code(0x92); - setup_ioapic(); -#endif /* IOAPIC */ // generic mainboard fixup mainboard_fixup(); #ifndef MAINBOARD_FIXUP_IN_CHARGE + post_code(0x91); + setup_i8259(); + + /* set up the IO-APIC for the clock interrupt. */ + post_code(0x92); + setup_ioapic(); + nvram_on(); - intel_display_cpuid(); - intel_mtrr_check(); - - -#ifndef NO_KEYBOARD - keyboard_on(); -#endif /* NO_KEYBOARD */ #ifndef USE_NEW_SUPERIO_INTERFACE -#ifdef MUST_ENABLE_FLOPPY enable_floppy(); post_code(0x95); -#endif /* MUST_ENABLE_FLOPPY */ #endif + #ifdef USE_NEW_SUPERIO_INTERFACE handle_superio(1, all_superio, nsuperio); #endif -#ifdef SMP - /* copy the smp block to address 0 */ - intel_smpblock((void *)16); - post_code(0x96); -#endif /* SMP */ + pci_zero_irq_settings(); - intel_zero_irq_settings(); - intel_check_irq_routing_table(); - intel_copy_irq_routing_table(); + /* copy the smp block to address 0 */ + write_smp_table((void *)16); + post_code(0x96); + + check_pirq_routing_table(); + copy_pirq_routing_table(); post_code(0x9a); /* to do: intel_serial_on(); */ - intel_interrupts_on(); - -#ifdef FINAL_MAINBOARD_FIXUP - printk(KERN_INFO "Final mainboard fixup for "); - post_code(0xec); final_mainboard_fixup(); - printk(KERN_INFO "done.\n"); -#endif /* FINAL_MAINBOARD_FIXUP */ + post_code(0xec); -#ifdef CONFIGURE_L2_CACHE - /* now that everything is really up, enable the l2 cache if desired. - * The enable can wait until this point, because linuxbios and it's - * data areas are tiny, easily fitting into the L1 cache. - */ - printk(KERN_INFO "Configuring L2 cache..."); - intel_l2_configure(); - printk(KERN_INFO "done.\n"); -#endif /* CONFIGURE_L2_CACHE */ #endif /* MAINBOARD_FIXUP_IN_CHARGE */ #ifdef USE_NEW_SUPERIO_INTERFACE handle_superio(2, all_superio, nsuperio); #endif + /* make certain we are the only cpu running in linuxBIOS */ + wait_for_other_cpus(); #ifdef LINUXBIOS - printk(KERN_INFO "Jumping to linuxbiosmain()...\n"); + printk_info("Jumping to linuxbiosmain()...\n"); // we could go to argc, argv, for main but it seems like overkill. post_code(0xed); linuxbiosmain(0, totalram); diff --git a/src/arch/i386/lib/i386_subr.c b/src/arch/i386/lib/i386_subr.c index 4bfb1fe0f9..e24614933d 100644 --- a/src/arch/i386/lib/i386_subr.c +++ b/src/arch/i386/lib/i386_subr.c @@ -1,16 +1,19 @@ #include #include #include - +#include +#include #include #include #include #include -#include +#include -void intel_cache_on(unsigned long base, unsigned long totalram) +void cache_on(unsigned long totalram) { post_code(0x60); + printk_info("Enabling cache..."); + /* we need an #ifdef i586 here at some point ... */ __asm__ __volatile__("mov %cr0, %eax\n\t" @@ -22,15 +25,17 @@ void intel_cache_on(unsigned long base, unsigned long totalram) * so absolute minimum needed to get it going. */ /* OK, linux it turns out does nothing. We have to do it ... */ -#ifdef i686 +#if defined(i686) // totalram here is in linux sizing, i.e. units of KB. // set_mtrr is responsible for getting it into the right units! - intel_set_mtrr(base, totalram); + setup_mtrrs(totalram); #endif + post_code(0x6A); + printk_info("done.\n"); } -void intel_interrupts_on() +void interrupts_on() { /* this is so interrupts work. This is very limited scope -- * linux will do better later, we hope ... @@ -39,128 +44,57 @@ void intel_interrupts_on() * stuff. So we have to do things differently ... * see the Intel mp1.4 spec, page A-3 */ -#ifdef SMP - unsigned long reg, *regp; -#define SVR 0xfee000f0 -#define LVT1 0xfee00350 -#define LVT2 0xfee00360 -#define APIC_ENABLED 0x100 - printk(KERN_INFO "Enabling interrupts..."); - - regp = (unsigned long *) SVR; - reg = *regp; - reg &= (~0xf0); - reg |= APIC_ENABLED; - *regp = reg; - - regp = (unsigned long *) LVT1; - reg = *regp; - reg &= 0xfffe00ff; - reg |= 0x5700; - *regp = reg; - - regp = (unsigned long *) LVT2; - reg = *regp; - reg &= 0xfffe00ff; - reg |= 0x5400; - *regp = reg; -#else /* !SMP */ -#ifdef i686 - /* Only Pentium Pro and later have thos MSR stuff */ +#if defined(SMP) + /* Only Pentium Pro and later have those MSR stuff */ unsigned long low, high; - printk(KERN_INFO "Enabling interrupts..."); + printk_info("Setting up local apic..."); - rdmsr(0x1b, low, high); - low &= ~0x800; - wrmsr(0x1b, low, high); + /* Enable the local apic */ + rdmsr(APIC_BASE_MSR, low, high); + low |= APIC_BASE_MSR_ENABLE; + low &= ~APIC_BASE_MSR_ADDR_MASK; + low |= APIC_DEFAULT_BASE; + wrmsr(APIC_BASE_MSR, low, high); + + + /* Put the local apic in virtual wire mode */ + apic_write_around(APIC_SPIV, + (apic_read_around(APIC_SPIV) & ~(APIC_VECTOR_MASK)) + | APIC_SPIV_ENABLE); + apic_write_around(APIC_LVT0, + (apic_read_around(APIC_LVT0) & + ~(APIC_LVT_MASKED | APIC_LVT_LEVEL_TRIGGER | + APIC_LVT_REMOTE_IRR | APIC_INPUT_POLARITY | + APIC_SEND_PENDING |APIC_LVT_RESERVED_1 | + APIC_DELIVERY_MODE_MASK)) + | (APIC_LVT_REMOTE_IRR |APIC_SEND_PENDING | + APIC_DELIVERY_MODE_EXTINT) + ); + apic_write_around(APIC_LVT1, + (apic_read_around(APIC_LVT1) & + ~(APIC_LVT_MASKED | APIC_LVT_LEVEL_TRIGGER | + APIC_LVT_REMOTE_IRR | APIC_INPUT_POLARITY | + APIC_SEND_PENDING |APIC_LVT_RESERVED_1 | + APIC_DELIVERY_MODE_MASK)) + | (APIC_LVT_REMOTE_IRR |APIC_SEND_PENDING | + APIC_DELIVERY_MODE_NMI) + ); +#else /* SMP */ +#ifdef i686 + /* Only Pentium Pro and later have those MSR stuff */ + unsigned long low, high; + + printk_info("Disabling local apic..."); + + rdmsr(APIC_BASE_MSR, low, high); + low &= ~APIC_BASE_MSR_ENABLE; + wrmsr(APIC_BASE_MSR, low, high); #endif /* i686 */ #endif /* SMP */ - - printk(KERN_INFO "done.\n"); + printk_info("done.\n"); post_code(0x9b); } -/* These functions should be chip-set independent -tds */ -void intel_zero_irq_settings(void) -{ - struct pci_dev *pcidev; - unsigned char line; - - printk(KERN_INFO "Zeroing IRQ settings..."); - - pcidev = pci_devices; - - while (pcidev) { - pci_read_config_byte(pcidev, 0x3d, &line); - if (line) { - pci_write_config_byte(pcidev, 0x3c, 0); - } - pcidev = pcidev->next; - } - printk(KERN_INFO "done.\n"); -} - -void intel_check_irq_routing_table(void) -{ -#ifdef HAVE_PIRQ_TABLE - const u8 *addr; - const struct irq_routing_table *rt; - int i; - u8 sum; - - printk(KERN_INFO "Checking IRQ routing tables..."); - - rt = &intel_irq_routing_table; - addr = (u8 *)rt; - - sum = 0; - for (i = 0; i < rt->size; i++) - sum += addr[i]; - - DBG("%s:%6d:%s() - irq_routing_table located at: 0x%p\n", - __FILE__, __LINE__, __FUNCTION__, addr); - - sum = (unsigned char)(rt->checksum-sum); - - if (sum != rt->checksum) { - printk(KERN_WARNING "%s:%6d:%s() - " - "checksum is: 0x%02x but should be: 0x%02x\n", - __FILE__, __LINE__, __FUNCTION__, rt->checksum, sum); - } - - if (rt->signature != PIRQ_SIGNATURE || rt->version != PIRQ_VERSION || - rt->size % 16 || rt->size < sizeof(struct irq_routing_table)) { - printk(KERN_WARNING "%s:%6d:%s() - " - "Interrupt Routing Table not valid\n", - __FILE__, __LINE__, __FUNCTION__); - return; - } - - sum = 0; - for (i=0; isize; i++) - sum += addr[i]; - - if (sum) { - printk(KERN_WARNING "%s:%6d:%s() - " - "checksum error in irq routing table\n", - __FILE__, __LINE__, __FUNCTION__); - } - - printk(KERN_INFO "done.\n"); -#endif /* #ifdef HAVE_PIRQ_TABLE */ -} - -#define RTABLE_DEST 0xf0000 - -void intel_copy_irq_routing_table(void) -{ -#ifdef HAVE_PIRQ_TABLE - printk(KERN_INFO "Copying IRQ routing tables..."); - memcpy((char *) RTABLE_DEST, &intel_irq_routing_table, intel_irq_routing_table.size); - printk(KERN_INFO "done.\n"); -#endif -} - diff --git a/src/cpu/k7/cpufixup.c b/src/cpu/k7/cpufixup.c index 8fa2209b53..60e75e728b 100644 --- a/src/cpu/k7/cpufixup.c +++ b/src/cpu/k7/cpufixup.c @@ -1,6 +1,7 @@ // Needed so the AMD K7 runs correctly. #include #include +#include #define TOP_MEM 0xc001001a #define TOP_MEM2 0xc001001d @@ -10,34 +11,34 @@ #define MTRRVARDRAMEN (1 << 20) void -cpufixup(unsigned long ram_kilobytes) +k7_cpufixup(unsigned long ram_kilobytes) { - unsigned long lo = 0, hi = 0, i; - unsigned long ram_megabytes = ram_kilobytes * 1024; + unsigned long lo = 0, hi = 0, i; + unsigned long ram_megabytes = ram_kilobytes * 1024; // 8 MB alignment please - ram_megabytes += 0x7fffff; - ram_megabytes &= (~0x7fffff); - // set top_mem registers to ram size - printk(KERN_INFO "Setting top_mem to 0x%x\n", ram_megabytes); - rdmsr(TOP_MEM, lo, hi); - printk(KERN_INFO "TOPMEM was 0x%x:0x$x\n", hi, lo); - hi = 0; - lo = ram_megabytes; - wrmsr(TOP_MEM, lo, hi); - // I am setting this even though I won't enable it - wrmsr(TOP_MEM2, lo, hi); - - /* zero the IORR's before we enable to prevent - * undefined side effects - */ - lo = hi = 0; - for(i = IORR_FIRST; i <= IORR_LAST; i++) - wrmsr(i, lo, hi); - - rdmsr(SYSCFG, lo, hi); - printk(KERN_INFO "SYSCFG was 0x%x:0x%x\n", hi, lo); - lo |= MTRRVARDRAMEN; - wrmsr(SYSCFG, lo, hi); - rdmsr(SYSCFG, lo, hi); - printk(KERN_INFO "SYSCFG IS NOW 0x%x:0x%x\n", hi, lo); + ram_megabytes += 0x7fffff; + ram_megabytes &= (~0x7fffff); + // set top_mem registers to ram size + printk_spew("Setting top_mem to 0x%x\n", ram_megabytes); + rdmsr(TOP_MEM, lo, hi); + printk_spew("TOPMEM was 0x%02x:0x%02x\n", hi, lo); + hi = 0; + lo = ram_megabytes; + wrmsr(TOP_MEM, lo, hi); + // I am setting this even though I won't enable it + wrmsr(TOP_MEM2, lo, hi); + + /* zero the IORR's before we enable to prevent + * undefined side effects + */ + lo = hi = 0; + for(i = IORR_FIRST; i <= IORR_LAST; i++) + wrmsr(i, lo, hi); + + rdmsr(SYSCFG, lo, hi); + printk_spew("SYSCFG was 0x%x:0x%x\n", hi, lo); + lo |= MTRRVARDRAMEN; + wrmsr(SYSCFG, lo, hi); + rdmsr(SYSCFG, lo, hi); + printk_spew("SYSCFG IS NOW 0x%x:0x%x\n", hi, lo); } diff --git a/src/cpu/p5/cpuid.c b/src/cpu/p5/cpuid.c index 3d627a595b..7be24baa62 100644 --- a/src/cpu/p5/cpuid.c +++ b/src/cpu/p5/cpuid.c @@ -12,30 +12,30 @@ static char rcsid[] = "$Id$"; #endif -int intel_mtrr_check(void) +int mtrr_check(void) { #ifdef i686 /* Only Pentium Pro and later have MTRR */ unsigned long low, high; - DBG("\nMTRR check\n"); + printk_debug("\nMTRR check\n"); rdmsr(0x2ff, low, high); low = low >> 10; - DBG("Fixed MTRRs : "); + printk_debug("Fixed MTRRs : "); if (low & 0x01) - DBG("Enabled\n"); + printk_debug("Enabled\n"); else - DBG("Disabled\n"); + printk_debug("Disabled\n"); - DBG("Variable MTRRs: "); + printk_debug("Variable MTRRs: "); if (low & 0x02) - DBG("Enabled\n"); + printk_debug("Enabled\n"); else - DBG("Disabled\n"); + printk_debug("Disabled\n"); - DBG("\n"); + printk_debug("\n"); post_code(0x93); return ((int) low); @@ -44,46 +44,46 @@ int intel_mtrr_check(void) #endif /* i686 */ } -void intel_display_cpuid(void) +void display_cpuid(void) { int op, eax, ebx, ecx, edx; int max_op; max_op = 0; - DBG("\n"); + printk_debug("\n"); for (op = 0; op <= max_op; op++) { - intel_cpuid(op, &eax, &ebx, &ecx, &edx); + cpuid(op, &eax, &ebx, &ecx, &edx); if (0 == op) { max_op = eax; - DBG("Max cpuid index : %d\n", eax); - DBG("Vendor ID : " + printk_debug("Max cpuid index : %d\n", eax); + printk_debug("Vendor ID : " "%c%c%c%c%c%c%c%c%c%c%c%c\n", ebx, ebx >> 8, ebx >> 16, ebx >> 24, edx, edx >> 8, edx >> 16, edx >> 24, ecx, ecx >> 8, ecx >> 16, ecx >> 24); } else if (1 == op) { - DBG("Processor Type : 0x%02x\n", + printk_debug("Processor Type : 0x%02x\n", (eax >> 12) & 0x03); - DBG("Processor Family : 0x%02x\n", + printk_debug("Processor Family : 0x%02x\n", (eax >> 8) & 0x0f); - DBG("Processor Model : 0x%02x\n", + printk_debug("Processor Model : 0x%02x\n", (eax >> 4) & 0x0f); - DBG("Processor Mask : 0x%02x\n", + printk_debug("Processor Mask : 0x%02x\n", (ecx >> 0) & 0x0f); - DBG("Processor Stepping : 0x%02x\n", + printk_debug("Processor Stepping : 0x%02x\n", (eax >> 0) & 0x0f); - DBG("Feature flags : 0x%08x\n", edx); + printk_debug("Feature flags : 0x%08x\n", edx); } else if (2 == op) { int desc[4]; int ii; int _desc; - DBG("\n"); + printk_debug("\n"); - DBG("Cache/TLB descriptor values: %d " + printk_debug("Cache/TLB descriptor values: %d " "reads required\n", eax & 0xff); desc[0] = eax; @@ -93,133 +93,133 @@ void intel_display_cpuid(void) for (ii = 1; ii < 16; ii++) { if (desc[ii >> 2] & 0x80000000) { - DBG("reserved descriptor\n"); + printk_debug("reserved descriptor\n"); continue; } _desc = ((desc[ii >> 2]) >> ((ii & 0x3) << 3)) & 0xff; - DBG("Desc 0x%02x : ", _desc); + printk_debug("Desc 0x%02x : ", _desc); switch (_desc) { case 0x00: - DBG("null\n"); + printk_debug("null\n"); break; case 0x01: - DBG("Instr TLB: " + printk_debug("Instr TLB: " "4KB pages, " "4-way set assoc, " "32 entries\n"); break; case 0x02: - DBG("Instr TLB: " + printk_debug("Instr TLB: " "4MB pages, " "fully assoc, " "2 entries\n"); break; case 0x03: - DBG("Data TLB: " + printk_debug("Data TLB: " "4KB pages, " "4-way set assoc, " "64 entries\n"); break; case 0x04: - DBG("Data TLB: " + printk_debug("Data TLB: " "4MB pages, " "4-way set assoc, " "8 entries\n"); break; case 0x06: - DBG("Inst cache: " + printk_debug("Inst cache: " "8K bytes, " "4-way set assoc, " "32 byte line size\n"); break; case 0x08: - DBG("Inst cache: " + printk_debug("Inst cache: " "16K bytes, " "4-way set assoc, " "32 byte line size\n"); break; case 0x0a: - DBG("Data cache: " + printk_debug("Data cache: " "8K bytes, " "2-way set assoc, " "32 byte line size\n"); break; case 0x0c: - DBG("Data cache: " + printk_debug("Data cache: " "16K bytes, " "2-way or 4-way set assoc, " "32 byte line size\n"); break; case 0x40: - DBG("No L2 cache\n"); + printk_debug("No L2 cache\n"); break; case 0x41: - DBG("L2 Unified cache: " + printk_debug("L2 Unified cache: " "128K bytes, " "4-way set assoc, " "32 byte line size\n"); break; case 0x42: - DBG("L2 Unified cache: " + printk_debug("L2 Unified cache: " "256K bytes, " "4-way set assoc, " "32 byte line size\n"); break; case 0x43: - DBG("L2 Unified cache: " + printk_debug("L2 Unified cache: " "512K bytes, " "4-way set assoc, " "32 byte line size\n"); break; case 0x44: - DBG("L2 Unified cache: " + printk_debug("L2 Unified cache: " "1M byte, " "4-way set assoc, " "32 byte line size\n"); break; case 0x45: - DBG("L2 Unified cache: " + printk_debug("L2 Unified cache: " "2M byte, " "4-way set assoc, " "32 byte line size\n"); break; case 0x82: - DBG("L2 Unified cache: " + printk_debug("L2 Unified cache: " "256K bytes, " "8-way set assoc, " "32 byte line size\n"); break; default: - DBG("UNKNOWN\n"); + printk_debug("UNKNOWN\n"); } } - DBG("\n"); + printk_debug("\n"); } else { - DBG("op: 0x%02x eax:0x%08x " + printk_debug("op: 0x%02x eax:0x%08x " "ebx:0x%08x ecx:0x%08x edx:0x%08x\n", op, eax, ebx, ecx, edx); } } - DBG("\n"); + printk_debug("\n"); post_code(0x92); } diff --git a/src/cpu/p6/Config b/src/cpu/p6/Config index 4b09cd3b73..def8b5b766 100644 --- a/src/cpu/p6/Config +++ b/src/cpu/p6/Config @@ -1,7 +1,5 @@ option i686 option INTEL_PPRO_MTRR object microcode.o -object mpspec.o object mtrr.o object l2_cache.o -object ioapic.o diff --git a/src/cpu/p6/earlymtrr.inc b/src/cpu/p6/earlymtrr.inc index 32920c7dfe..4ef4b43260 100644 --- a/src/cpu/p6/earlymtrr.inc +++ b/src/cpu/p6/earlymtrr.inc @@ -1,23 +1,27 @@ #include /* The fixed and variable MTRRs are powered-up with random values, clear them to - * MTRR_TYPE_UNCACHABLE for safty reason */ + * MTRR_TYPE_UNCACHABLE for safty reason + */ + earlymtrr_start: xorl %eax, %eax # clear %eax and %edx xorl %edx, %edx # movl $fixed_mtrr_msr, %esi clear_fixed_var_mtrr: - lodsw (%esi), %ax - testw $0x00, %ax - jz set_fixed_mtrr + lodsl (%esi), %eax + testl %eax, %eax + jz clear_fixed_var_mtrr_out - movzwl %ax, %ecx + movl %eax, %ecx xorl %eax, %eax wrmsr jmp clear_fixed_var_mtrr +clear_fixed_var_mtrr_out: +#ifdef MEMORY_HOLE set_fixed_mtrr: /* enable Write Back Cache for 0-640KB */ movl $MTRRfix64K_00000_MSR, %ecx @@ -31,51 +35,71 @@ set_fixed_mtrr: movl $0x06060606, %edx movl $0x06060606, %eax wrmsr +#endif /* MEMORY_HOLE */ set_var_mtrr: - /* enable caching for 0-2(or 4)MB using variable mtrr */ - mov $0x200, %ecx + /* enable caching for 0 - 128MB using variable mtrr */ + movl $0x200, %ecx rdmsr - and $0xfffffff0, %edx - or $0x00000000, %edx - and $0x00000f00, %eax - or $0x00000006, %eax + andl $0xfffffff0, %edx + orl $0x00000000, %edx + andl $0x00000f00, %eax + orl $0x00000006, %eax wrmsr - mov $0x201, %ecx + movl $0x201, %ecx rdmsr - and $0xfffffff0, %edx - or $0x0000000f, %edx - and $0x000007ff, %eax - or $0xf0000800, %eax + andl $0xfffffff0, %edx + orl $0x0000000f, %edx + andl $0x000007ff, %eax + orl $0xf0000800, %eax wrmsr +#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) + /* enable write protect caching so we can do execute in place + * on the flash rom. + */ + movl $0x202, %ecx + xorl %edx, %edx + movl $(XIP_ROM_BASE | 0x005), %eax + wrmsr + + movl $0x203, %ecx + movl $0x0000000f, %edx + movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax + wrmsr +#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ + enable_mtrr: /* Set the default memory type and enable fixed and variable MTRRs */ movl $0x2ff, %ecx - rdmsr - and $0xfffff300, %eax + xorl %edx, %edx +#ifdef MEMORY_HOLE /* Enable Fixed and Variable MTRRs */ - or $0x00000c00, %eax + movl $0x00000c00, %eax +#else + /* Enable Variable MTRRs */ + movl $0x00000800, %eax +#endif /* MEMORY_HOLE */ wrmsr /* enable cache */ - mov %cr0, %eax - and $0x9fffffff,%eax - mov %eax, %cr0 + movl %cr0, %eax + andl $0x9fffffff,%eax + movl %eax, %cr0 jmp earlymtrr_end fixed_mtrr_msr: - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F + .long 0x250, 0x258, 0x259 + .long 0x268, 0x269, 0x26A + .long 0x26B, 0x26C, 0x26D + .long 0x26E, 0x26F var_mtrr_msr: - .word 0x200, 0x201, 0x202, 0x203 - .word 0x204, 0x205, 0x206, 0x207 - .word 0x208, 0x209, 0x20A, 0x20B - .word 0x20C, 0x20D, 0x20E, 0x20F - .word 0x000 /* NULL, end of table */ + .long 0x200, 0x201, 0x202, 0x203 + .long 0x204, 0x205, 0x206, 0x207 + .long 0x208, 0x209, 0x20A, 0x20B + .long 0x20C, 0x20D, 0x20E, 0x20F + .long 0x000 /* NULL, end of table */ earlymtrr_end: diff --git a/src/cpu/p6/l2_cache.c b/src/cpu/p6/l2_cache.c index caf5d7a38c..f9aa6b56a6 100644 --- a/src/cpu/p6/l2_cache.c +++ b/src/cpu/p6/l2_cache.c @@ -61,7 +61,7 @@ void cache_disable(void) unsigned int tmp; /* Disable cache */ - DBG("Disable Cache\n"); + printk_debug("Disable Cache\n"); /* Write back the cache and flush TLB */ asm volatile ("movl %%cr0, %0\n\t" @@ -81,37 +81,39 @@ void cache_enable(void) "movl %0, %%cr0\n\t" :"=r" (tmp) : : "memory"); - DBG("Enable Cache\n"); + printk_debug("Enable Cache\n"); } // GOTO bad and GOTO done added by rgm. // there were too many ways that you could leave this thing with the // cache turned off! // TODO: save whether it was on or not, and restore that state on exit. -int intel_l2_configure() +int p6_configure_l2_cache() { unsigned int eax, ebx, ecx, edx; int signature, tmp; int cache_size; + int result; - intel_cpuid(0, &eax, &ebx, &ecx, &edx); + printk_info("Configuring L2 cache..."); + cpuid(0, &eax, &ebx, &ecx, &edx); if (ebx != 0x756e6547 || edx != 0x49656e69 || ecx != 0x6c65746e) { - printk(KERN_ERR "Not 'GenuineIntel' Processor\n"); + printk_err( "Not 'GenuineIntel' Processor\n"); goto bad; } - intel_cpuid(1, &eax, &ebx, &ecx, &edx); + cpuid(1, &eax, &ebx, &ecx, &edx); /* Mask out the stepping */ signature = eax & 0xfff0; if (signature & 0x1000) { - DBG("Overdrive chip no L2 cache configuration\n"); + printk_debug("Overdrive chip no L2 cache configuration\n"); goto done; } if (signature < 0x630 || signature >= 0x680) { - DBG("CPU signature of %x so no L2 cache configuration\n", + printk_debug("CPU signature of %x so no L2 cache configuration\n", signature); goto done; } @@ -120,7 +122,7 @@ int intel_l2_configure() rdmsr(BBL_CR_CTL3, eax, edx); /* If bit 23 (L2 Hardware disable) is set then done */ if (eax & 0x800000) { - DBG("L2 Hardware disabled\n"); + printk_debug("L2 Hardware disabled\n"); goto done; } @@ -133,7 +135,7 @@ int intel_l2_configure() /* Mask out [22-24] Clock frequency ratio */ eax &= 0x1c00000; if (eax == 0xc00000 || eax == 0x1000000) { - printk(KERN_ERR "Incorrect clock frequency ratio %x\n", + printk_err( "Incorrect clock frequency ratio %x\n", eax); goto bad; } @@ -173,7 +175,7 @@ int intel_l2_configure() /* Mask out [22-24] Clock frequency ratio */ eax &= 0x3c00000; if (eax == 0xc00000 || eax == 0x3000000) { - printk(KERN_ERR "Incorrect clock frequency ratio %x\n", + printk_err( "Incorrect clock frequency ratio %x\n", eax); goto bad; } @@ -220,7 +222,7 @@ int intel_l2_configure() /* Shift to [1:0] */ v >>= 26; - DBG("Sending %x to set_l2_register4\n", v); + printk_debug("Sending %x to set_l2_register4\n", v); if (set_l2_register4(v) != 0) goto bad; @@ -231,7 +233,7 @@ int intel_l2_configure() /* Read L2 register 0 */ tmp = read_l2(0); if (tmp < 0) { - printk(KERN_ERR "Failed to read_l2(0)\n"); + printk_err("Failed to read_l2(0)\n"); goto bad; } @@ -246,18 +248,18 @@ int intel_l2_configure() } if (calculate_l2_ecc() != 0) { - printk(KERN_ERR "Failed to calculate L2 ECC\n"); + printk_err( "Failed to calculate L2 ECC\n"); goto bad; } if (calculate_l2_physical_address_range() != 0) { - printk(KERN_ERR + printk_err( "Failed to calculate L2 physical address range\n"); goto bad; } if (calculate_l2_cache_size() != 0) { - printk(KERN_ERR "Failed to calculate L2 cache size\n"); + printk_err("Failed to calculate L2 cache size\n"); goto bad; } @@ -272,7 +274,7 @@ int intel_l2_configure() cache_size = cache_size << 3; /* Cache is 4 way for each address */ - DBG("L2 Cache size is %dK\n", cache_size * 4 / 1024); + printk_debug("L2 Cache size is %dK\n", cache_size * 4 / 1024); /* Write to all cache lines to initialize */ while (cache_size > 0) { @@ -287,14 +289,14 @@ int intel_l2_configure() * MESI = Invalid */ if (signal_l2(0, cache_size, 0, 0, way, 0x1c) != 0) { - printk(KERN_ERR + printk_err( "Failed on signal_l2(%x, %x)\n", cache_size, way); goto bad; } } } - DBG("L2 Cache lines initialized\n"); + printk_debug("L2 Cache lines initialized\n"); /* Disable cache */ cache_disable(); @@ -309,7 +311,7 @@ int intel_l2_configure() /* Write 0 to L2 control register 5 */ if (write_l2(5, 0) != 0) { - printk(KERN_ERR "write_l2(5, 0) failed\n"); + printk_err("write_l2(5, 0) failed\n"); goto done; } @@ -333,13 +335,15 @@ int intel_l2_configure() /* Turn on cache. Both L1 and L2 are now active. Wahoo! */ done: + result = 0; + out: cache_enable(); - return 0; + printk_info("done.\n"); + return result; bad: - // it was probably on when we got here, so turn it back on. - cache_enable(); - return -1; + result = -1; + goto out; } /* Setup address_high:address_low, data_high:data_low into the L2 @@ -536,7 +540,7 @@ static int calculate_l2_latency(void) /* Read an undocumented MSR */ rdmsr(0x17, eax, edx); - DBG("rdmsr(0x17) = %x, %x\n", eax, edx); + printk_debug("rdmsr(0x17) = %x, %x\n", eax, edx); /* Mask out [23:20] in EDX. Are Intel trying to hide this?? */ edx &= 0x1e00000; @@ -565,12 +569,12 @@ static int calculate_l2_latency(void) else return -1; - intel_cpuid(1, &eax, &ebx, &ecx, &edx); + cpuid(1, &eax, &ebx, &ecx, &edx); /* Mask out Model/Type */ eax &= 0xfff0; - DBG("L2 latency type = %x\n", t); + printk_debug("L2 latency type = %x\n", t); if (eax == 0x650) { /* Read EBL_CR_POWERON */ @@ -597,13 +601,13 @@ static int calculate_l2_latency(void) } else return -1; - DBG("Searching for key %x\n", eax); + printk_debug("Searching for key %x\n", eax); /* Search table for matching entry */ for (le = latency_table; le->key != eax; le++) { /* Fail if we get to the end of the table */ if (le->key == 0xff) { - printk(KERN_ERR + printk_err( "Could not find key %x in latency table\n", eax); return -1; @@ -613,7 +617,7 @@ static int calculate_l2_latency(void) l = le->value; } - DBG("L2 Cache latency is %d\n", l / 2); + printk_debug("L2 Cache latency is %d\n", l / 2); /* Read BBL_CR_CTL3 */ rdmsr(0x11e, eax, edx); @@ -709,7 +713,7 @@ static int calculate_l2_cache_size(void) /* Write new value into BBL_CR_CTL3 */ wrmsr(0x11e, eax, edx); - DBG("Maximum cache mask is %x\n", cache_setting); + printk_debug("Maximum cache mask is %x\n", cache_setting); /* Write aaaaaaaa:aaaaaaaa to address 0 in the l2 cache */ v = test_l2_address_alias(0, 0, 0xaaaaaaaa, 0xaaaaaaaa); @@ -753,14 +757,14 @@ static int calculate_l2_cache_size(void) /* Write cache size into BBL_CR_CTL3 */ wrmsr(0x11e, eax, edx); - DBG("L2 Cache Mask is %x\n", size); + printk_debug("L2 Cache Mask is %x\n", size); /* Shift to [6:2] */ size >>= 11; v = read_l2(2); - DBG("read_l2(2) = %x\n", v); + printk_debug("read_l2(2) = %x\n", v); if (v < 0) return -1; @@ -773,7 +777,7 @@ static int calculate_l2_cache_size(void) /* Or in this size */ v |= size; - DBG("write_l2(2) = %x\n", v); + printk_debug("write_l2(2) = %x\n", v); if (write_l2(2, v) != 0) return -1; @@ -782,7 +786,7 @@ static int calculate_l2_cache_size(void) a = read_l2(2); - DBG("read_l2(2) = %x\n", a); + printk_debug("read_l2(2) = %x\n", a); if (a < 0) return -1; @@ -794,7 +798,7 @@ static int calculate_l2_cache_size(void) a &= 0xf; - DBG("Calculated a = %x\n", a); + printk_debug("Calculated a = %x\n", a); if (a == 0) return -1; @@ -836,7 +840,7 @@ static int calculate_l2_physical_address_range(void) else r3 &= 0x7; - DBG("L2 Physical Address Range is %dM\n", (1 << r3) * 512); + printk_debug("L2 Physical Address Range is %dM\n", (1 << r3) * 512); /* Shift into [22:20] */ r3 = r3 << 20; @@ -877,7 +881,7 @@ static int calculate_l2_ecc(void) rdmsr(0x118, eax, edx); if (eax == data1) { - DBG("L2 ECC Checking is enabled\n"); + printk_debug("L2 ECC Checking is enabled\n"); /* Set ECC Check Enable in BBL_CR_CTL3 */ rdmsr(0x11e, eax, edx); diff --git a/src/cpu/p6/microcode.c b/src/cpu/p6/microcode.c index 4364c5e054..53b9d0ccf2 100644 --- a/src/cpu/p6/microcode.c +++ b/src/cpu/p6/microcode.c @@ -12,6 +12,7 @@ static char rcsid[] = "$Id$"; #include #include #include +#include struct microcode { unsigned int hdrver; @@ -299,7 +300,7 @@ unsigned int microcode_updates [] = { 0x57688086, 0x218e4005, 0xca054e3d, 0xc1a3c3ec, }; -void intel_display_cpuid_microcode(void) +static void display_cpuid_update_microcode(void) { unsigned int eax, ebx, ecx, edx; unsigned int pf, rev, sig, val[2]; @@ -308,7 +309,7 @@ void intel_display_cpuid_microcode(void) /* cpuid sets msr 0x8B iff a microcode update has been loaded. */ wrmsr(0x8B, 0, 0); - intel_cpuid(1, &eax, &ebx, &ecx, &edx); + cpuid(1, &eax, &ebx, &ecx, &edx); rdmsr(0x8B, val[0], rev); x86_model = (eax >>4) & 0x0f; sig = eax; @@ -318,7 +319,7 @@ void intel_display_cpuid_microcode(void) rdmsr(0x17, val[0], val[1]); pf = 1 << ((val[1] >> 18) & 7); } - printk(KERN_INFO "microcode_info: sig = 0x%08x pf=0x%08x rev = 0x%08x\n", + printk_info("microcode_info: sig = 0x%08x pf=0x%08x rev = 0x%08x\n", sig, pf, rev); m = (void *)µcode_updates; @@ -327,8 +328,14 @@ void intel_display_cpuid_microcode(void) wrmsr(0x79, (unsigned int)&m[i].bits, 0); __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx"); rdmsr(0x8B, val[0], val[1]); - printk(KERN_INFO "microcode updated from revision %d to %d\n", + printk_info("microcode updated from revision %d to %d\n", rev, val[1]); } } } + +void p6_cpufixup(unsigned long totalram) +{ + printk_info("Updating microcode\n"); + display_cpuid_update_microcode(); +} diff --git a/src/cpu/p6/mtrr.c b/src/cpu/p6/mtrr.c index 8d0a0cad00..07269f3628 100644 --- a/src/cpu/p6/mtrr.c +++ b/src/cpu/p6/mtrr.c @@ -31,6 +31,7 @@ static char rcsid[] = "$Id$"; #include #include +#include #include #include @@ -44,58 +45,76 @@ static unsigned int mtrr_msr[] = { #ifndef HAVE_MTRR_TABLE +/* We want to cache memory as efficiently as possible. + */ +#define MTRR_TYPE_RAM MTRR_TYPE_WRBACK +/* We can't use Write Combining on a legacy frame buffer because + * it is incompatible with EGA 16 color video modes... + */ +#define MTRR_TYPE_FB MTRR_TYPE_UNCACHABLE +/* For areas that are supposed to cover roms it makes no + * sense to cache writes. + */ +#define MTRR_TYPE_ROM MTRR_TYPE_WRPROT + + +#ifdef MEMORY_HOLE +#define RAM MTRR_TYPE_RAM +#define FB MTRR_TYPE_FB +#define ROM MTRR_TYPE_ROM +#else +#define RAM MTRR_TYPE_RAM +#define FB MTRR_TYPE_RAM +#define ROM MTRR_TYPE_RAM +#endif /* MEMORY_HOLE */ + static unsigned char fixed_mtrr_values[][4] = { /* MTRRfix64K_00000_MSR, defines memory range from 0KB to 512 KB, each byte cover 64KB area */ - {MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK}, - {MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK}, + {RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM}, /* MTRRfix16K_80000_MSR, defines memory range from 512KB to 640KB, each byte cover 16KB area */ - {MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK}, - {MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK}, + {RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM}, /* MTRRfix16K_A0000_MSR, defines memory range from A0000 to C0000, each byte cover 16KB area */ - {MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB}, - {MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB}, + {FB, FB, FB, FB}, {FB, FB, FB, FB}, /* MTRRfix4K_C0000_MSR, defines memory range from C0000 to C8000, each byte cover 4KB area */ - {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, - {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + {ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM}, /* MTRRfix4K_C8000_MSR, defines memory range from C8000 to D0000, each byte cover 4KB area */ - {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, - {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + {ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM}, /* MTRRfix4K_D0000_MSR, defines memory range from D0000 to D8000, each byte cover 4KB area */ - {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, - {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + {ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM}, /* MTRRfix4K_D8000_MSR, defines memory range from D8000 to E0000, each byte cover 4KB area */ - {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, - {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + {ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM}, /* MTRRfix4K_E0000_MSR, defines memory range from E0000 to E8000, each byte cover 4KB area */ - {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, - {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + {ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM}, /* MTRRfix4K_E8000_MSR, defines memory range from E8000 to F0000, each byte cover 4KB area */ - {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, - {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + {ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM}, /* MTRRfix4K_F0000_MSR, defines memory range from F0000 to F8000, each byte cover 4KB area */ - {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, - {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + {ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM}, /* MTRRfix4K_F8000_MSR, defines memory range from F8000 to 100000, each byte cover 4KB area */ - {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, - {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + {ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM}, }; +#undef FB +#undef RAM +#undef ROM +#undef MTRR_TYPE_RAM +#undef MTRR_TYPE_FB +#undef MTRR_TYPE_ROM + #else extern unsigned char fixed_mtrr_values[][4]; #endif -void -intel_enable_fixed_mtrr() +static void intel_enable_fixed_mtrr(void) { unsigned long low, high; @@ -104,8 +123,7 @@ intel_enable_fixed_mtrr() wrmsr(MTRRdefType_MSR, low, high); } -void -intel_enable_var_mtrr() +static void intel_enable_var_mtrr(void) { unsigned long low, high; @@ -116,7 +134,7 @@ intel_enable_var_mtrr() /* setting fixed mtrr, you can do some experiments with different memory type defined in the table "fixed_mtrr_values" */ -void intel_set_fixed_mtrr() +static void intel_set_fixed_mtrr(void) { unsigned int i; unsigned long low, high; @@ -129,7 +147,7 @@ void intel_set_fixed_mtrr() } /* setting variable mtrr, comes from linux kernel source */ -void intel_set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size, unsigned char type) +static void intel_set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size, unsigned char type) { unsigned int tmp; @@ -197,28 +215,36 @@ static __inline__ unsigned int fms(unsigned int x) * ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB) */ #ifdef INTEL_PPRO_MTRR -#ifdef ENABLE_FIXED_AND_VARIABLE_MTRRS -void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK) + +/* 2 MTRRS are reserved for the operating system */ +#define BIOS_MTRRS 6 +#define OS_MTRRS 2 +#define MTRRS (BIOS_MTRRS + OS_MTRRS) + +void setup_mtrrs(unsigned long ramsizeK) { unsigned int reg = 0; unsigned long range_wb, range_uc; + unsigned long rambase; + unsigned long romendK; - DBG("\n"); + printk_debug("\n"); + rambase = 0; - while (ramsizeK != 0 && reg <= 6) { + while (ramsizeK != 0 && reg < BIOS_MTRRS) { post_code(0x60 + reg); range_wb = 1 << (fms(ramsizeK - 1) + 1); range_uc = range_wb - ramsizeK; if ((range_uc == 0) || ((ramsizeK % range_uc) == 0)) { - DBG("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type: WB\n", + printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type: WB\n", reg, rambase >> 10, range_wb >> 10); intel_set_var_mtrr(reg++, rambase * 1024, range_wb * 1024, MTRR_TYPE_WRBACK); rambase += ramsizeK; - DBG("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type: UC\n", + printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type: UC\n", reg, rambase >> 10, range_uc >> 10); intel_set_var_mtrr(reg++, rambase * 1024, range_uc * 1024, MTRR_TYPE_UNCACHABLE); @@ -226,7 +252,7 @@ void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK) } else { range_wb >>= 1; - DBG("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type: WB\n", + printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type: WB\n", reg, rambase >> 10, range_wb >> 10); intel_set_var_mtrr(reg++, rambase * 1024, range_wb * 1024, MTRR_TYPE_WRBACK); @@ -235,19 +261,34 @@ void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK) ramsizeK -= range_wb; } } - +#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) +#if XIP_ROM_SIZE < 4096 +#error XIP_ROM_SIZE must be at least 4K +#endif +#if XIP_ROM_SIZE & (XIP_ROM_SIZE -1) +#error XIP_ROM_SIZE must be a power of two +#endif +#if XIP_ROM_BASE & (XIP_ROM_SIZE -1) +#error XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +#endif + /* I assume that XIP_ROM_SIZE is a power of two + * and that XIP_ROM_BASE is power of tow aligned. + */ + romendK = (XIP_ROM_BASE + XIP_ROM_SIZE) >>10; + if ((reg < BIOS_MTRRS) && + ((XIP_ROM_BASE > rambase) || (romendK > rambase))) { + intel_set_var_mtrr(reg++, XIP_ROM_BASE, XIP_ROM_SIZE, + MTRR_TYPE_WRPROT); + } +#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ + /* Clear out the extra MTRR's */ + while(reg < MTRRS) { + intel_set_var_mtrr(reg++, 0, 0, 0); + } intel_set_fixed_mtrr(); /* enable fixed MTRR */ intel_enable_fixed_mtrr(); intel_enable_var_mtrr(); } -#else /* ENABLE_FIXED_AND_VARIABLE_MTRRS */ -void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK) -{ - DBG("\n"); - intel_set_var_mtrr(0, 0, ramsizeK * 1024, MTRR_TYPE_WRBACK); - intel_enable_var_mtrr(); -} -#endif /* ENABLE_FIXED_AND_VARIABLE_MTRRS */ #endif /* INTEL_PPRO_MTRR */ diff --git a/src/etherboot/netboot.c b/src/etherboot/netboot.c index 19c4f654c3..e12418098d 100644 --- a/src/etherboot/netboot.c +++ b/src/etherboot/netboot.c @@ -26,7 +26,7 @@ void init_HR_TIMER(void) outl(0x80000874, 0x0cf8); acpi_base = inw(0x0cfc); - printk("init_HR_TIMER: acpi_base = %04x\n", acpi_base); + printk_info("init_HR_TIMER: acpi_base = %04x\n", acpi_base); j = inw(acpi_base + 0x56) | 0x02; // HR_TMR control outw(j, acpi_base + 0x56); // activate HR_TMR @@ -47,18 +47,18 @@ int test_display_tftp_callback(char *data, int block, int length, int eof) int i; #ifdef DEBUG - printk("RECD block %u, length = %u:\n",block, length); + printk_info("RECD block %u, length = %u:\n",block, length); #endif for(i=0; i 0; tmo = 2*tmo+1); /* sleep */ - printk("\n"); + printk_info("\n"); for (tmo = (tmo&seed)+currticks(); currticks() < tmo; ) return; } @@ -351,7 +351,7 @@ int udp_transmit(unsigned long destip, unsigned int srcsock, for(arpentry = 0; arpentry\n"); + printk_info("\n"); #endif udp_transmit(arptable[ARP_SERVER].ipaddr.s_addr, iport, oport, @@ -453,7 +453,7 @@ int tftp(const char *name, int (*fnc)(unsigned char *, int, int, int)) tr = (struct tftp_t *)&nic.packet[ETH_HLEN]; if (tr->opcode == ntohs(TFTP_ERROR)) { - printk("TFTP error %d (%s)\n", + printk_info("TFTP error %d (%s)\n", ntohs(tr->u.err.errcode), tr->u.err.errmsg); break; @@ -587,7 +587,7 @@ int tftp_init(const char *name) if (block && ((retry += TFTP_REXMT) < TFTP_TIMEOUT)) { /* we resend our last ack */ #ifdef MDEBUG - printk("\n"); + printk_info("\n"); #endif udp_transmit(arptable[ARP_SERVER].ipaddr.s_addr, iport, oport, @@ -602,7 +602,7 @@ int tftp_init(const char *name) tr = (struct tftp_t *)&nic.packet[ETH_HLEN]; if (tr->opcode == ntohs(TFTP_ERROR)) { - printk("TFTP error %d (%s)\n", + printk_info("TFTP error %d (%s)\n", ntohs(tr->u.err.errcode), tr->u.err.errmsg); @@ -687,7 +687,7 @@ retry: if (block && ((retry += TFTP_REXMT) < TFTP_TIMEOUT)) { /* we resend our last ack */ #ifdef MDEBUG - printk("\n"); + printk_info("\n"); #endif udp_transmit(arptable[ARP_SERVER].ipaddr.s_addr, iport, oport, @@ -701,7 +701,7 @@ retry: tr = (struct tftp_t *)&nic.packet[ETH_HLEN]; if (tr->opcode == ntohs(TFTP_ERROR)) { - printk("TFTP error %d (%s)\n", + printk_info("TFTP error %d (%s)\n", ntohs(tr->u.err.errcode), tr->u.err.errmsg); return(-tr->u.err.errcode); diff --git a/src/etherboot/sis900.c b/src/etherboot/sis900.c index f2ca51e269..8159561c63 100644 --- a/src/etherboot/sis900.c +++ b/src/etherboot/sis900.c @@ -288,11 +288,11 @@ struct nic *sis900_probe(struct nic *nic, unsigned short *io_addrs, struct pci_d return NULL; } - printk("\nsis900_probe: MAC addr %02x:%02x:%02x:%02x:%02x:%02x at ioaddr %04x\n", + printk_info("\nsis900_probe: MAC addr %02x:%02x:%02x:%02x:%02x:%02x at ioaddr %04x\n", nic->node_addr[0],nic->node_addr[1],nic->node_addr[2], nic->node_addr[3],nic->node_addr[4],nic->node_addr[5], ioaddr); - printk("sis900_probe: Vendor:%04x Device:%04x\n", vendor, dev_id); + printk_info("sis900_probe: Vendor:%04x Device:%04x\n", vendor, dev_id); /* probe for mii transceiver */ /* search for total of 32 possible mii phy addresses */ @@ -315,7 +315,7 @@ struct nic *sis900_probe(struct nic *nic, unsigned short *io_addrs, struct pci_d if (phy_id0 == mii_chip_table[i].phy_id0) { - printk("sis900_probe: %s transceiver found at address %d.\n", + printk_info("sis900_probe: %s transceiver found at address %d.\n", mii_chip_table[i].name, phy_addr); mii.chip_info = &mii_chip_table[i]; @@ -326,19 +326,19 @@ struct nic *sis900_probe(struct nic *nic, unsigned short *io_addrs, struct pci_d found=1; break; } else { - printk("Found an MII, but can't recognize it. id= %u:%u\n", phy_id0, phy_id1); + printk_info("Found an MII, but can't recognize it. id= %u:%u\n", phy_id0, phy_id1); } } } if (found == 0) { - printk("sis900_probe: No MII transceivers found!\n"); + printk_info("sis900_probe: No MII transceivers found!\n"); return NULL; } /* Arbitrarily select the last PHY found as current PHY */ cur_phy = mii.phy_addr; - printk("sis900_probe: Using %s as default\n", mii.chip_info->name); + printk_info("sis900_probe: Using %s as default\n", mii.chip_info->name); /* initialize device */ sis900_init(nic); @@ -602,7 +602,7 @@ sis900_init_rxfilter(struct nic *nic) outl(w, ioaddr + rfdr); if (sis900_debug > 0) - printk("sis900_init_rxfilter: Receive Filter Addrss[%d]=%x\n", + printk_info("sis900_init_rxfilter: Receive Filter Addrss[%d]=%x\n", i, inl(ioaddr + rfdr)); } @@ -631,7 +631,7 @@ sis900_init_txd(struct nic *nic) /* load Transmit Descriptor Register */ outl((u32) &txd, ioaddr + txdp); if (sis900_debug > 0) - printk("sis900_init_txd: TX descriptor register loaded with: %X\n", + printk_info("sis900_init_txd: TX descriptor register loaded with: %X\n", inl(ioaddr + txdp)); } @@ -658,7 +658,7 @@ sis900_init_rxd(struct nic *nic) rxd[i].cmdsts = (u32) RX_BUF_SIZE; rxd[i].bufptr = (u32) &rxb[i*RX_BUF_SIZE]; if (sis900_debug > 0) - printk("sis900_init_rxd: rxd[%d]=%X link=%X cmdsts=%X bufptr=%X\n", + printk_info("sis900_init_rxd: rxd[%d]=%X link=%X cmdsts=%X bufptr=%X\n", i, &rxd[i], rxd[i].link, rxd[i].cmdsts, rxd[i].bufptr); } @@ -666,7 +666,7 @@ sis900_init_rxd(struct nic *nic) outl((u32) &rxd[0], ioaddr + rxdp); if (sis900_debug > 0) - printk("sis900_init_rxd: RX descriptor register loaded with: %X\n", + printk_info("sis900_init_rxd: RX descriptor register loaded with: %X\n", inl(ioaddr + rxdp)); } @@ -773,9 +773,9 @@ sis900_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex) *duplex = FDX_CAPABLE_HALF_SELECTED; if (status & MII_STSOUT_LINK_FAIL) - printk("sis900_read_mode: Media Link Off\n"); + printk_info("sis900_read_mode: Media Link Off\n"); else - printk("sis900_read_mode: Media Link On %s %s-duplex \n", + printk_info("sis900_read_mode: Media Link On %s %s-duplex \n", *speed == HW_SPEED_100_MBPS ? "100mbps" : "10mbps", *duplex == FDX_CAPABLE_FULL_SELECTED ? @@ -816,22 +816,22 @@ amd79c901_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex) *duplex = FDX_CAPABLE_HALF_SELECTED; if (status & MII_STSSUM_LINK) - printk("amd79c901_read_mode: Media Link On %s %s-duplex \n", + printk_info("amd79c901_read_mode: Media Link On %s %s-duplex \n", *speed == HW_SPEED_100_MBPS ? "100mbps" : "10mbps", *duplex == FDX_CAPABLE_FULL_SELECTED ? "full" : "half"); else - printk("amd79c901_read_mode: Media Link Off\n"); + printk_info("amd79c901_read_mode: Media Link Off\n"); } else { /* HomePNA */ *speed = HW_SPEED_HOME; *duplex = FDX_CAPABLE_HALF_SELECTED; if (status & MII_STAT_LINK) - printk("amd79c901_read_mode:Media Link On 1mbps half-duplex \n"); + printk_info("amd79c901_read_mode:Media Link On 1mbps half-duplex \n"); else - printk("amd79c901_read_mode: Media Link Off\n"); + printk_info("amd79c901_read_mode: Media Link Off\n"); } } @@ -867,13 +867,13 @@ static void ics1893_read_mode(struct nic *nic, int phy_addr, int *speed, int *du *duplex = FDX_CAPABLE_HALF_SELECTED; if (status & MII_STSICS_LINKSTS) - printk("ics1893_read_mode: Media Link On %s %s-duplex \n", + printk_info("ics1893_read_mode: Media Link On %s %s-duplex \n", *speed == HW_SPEED_100_MBPS ? "100mbps" : "10mbps", *duplex == FDX_CAPABLE_FULL_SELECTED ? "full" : "half"); else - printk("ics1893_read_mode: Media Link Off\n"); + printk_info("ics1893_read_mode: Media Link Off\n"); } /** @@ -911,13 +911,13 @@ static void rtl8201_read_mode(struct nic *nic, int phy_addr, int *speed, int *du } if (status & MII_STAT_LINK) - printk("rtl8201_read_mode: Media Link On %s %s-duplex \n", + printk_info("rtl8201_read_mode: Media Link On %s %s-duplex \n", *speed == HW_SPEED_100_MBPS ? "100mbps" : "10mbps", *duplex == FDX_CAPABLE_FULL_SELECTED ? "full" : "half"); else - printk("rtl9201_read_config_mode: Media Link Off\n"); + printk_info("rtl9201_read_config_mode: Media Link Off\n"); } /* Function: sis900_transmit @@ -948,7 +948,7 @@ sis900_transmit(struct nic *nic, /* load Transmit Descriptor Register */ outl((u32) &txd, ioaddr + txdp); if (sis900_debug > 1) - printk("sis900_transmit: TX descriptor register loaded with: %X\n", + printk_info("sis900_transmit: TX descriptor register loaded with: %X\n", inl(ioaddr + txdp)); memcpy(txb, d, ETH_ALEN); @@ -961,7 +961,7 @@ sis900_transmit(struct nic *nic, s &= DSIZE; if (sis900_debug > 1) - printk("sis900_transmit: sending %d bytes ethtype %x\n", (int) s, t); + printk_info("sis900_transmit: sending %d bytes ethtype %x\n", (int) s, t); /* pad to minimum packet size */ while (s < ETH_ZLEN) @@ -975,7 +975,7 @@ sis900_transmit(struct nic *nic, outl(TxENA, ioaddr + cr); if (sis900_debug > 1) - printk("sis900_transmit: Queued Tx packet size %d.\n", (int) s); + printk_info("sis900_transmit: Queued Tx packet size %d.\n", (int) s); to = currticks() + TX_TIMEOUT; @@ -983,12 +983,12 @@ sis900_transmit(struct nic *nic, /* wait */ ; if (currticks() >= to) { - printk("sis900_transmit: TX Timeout! Tx status %X.\n", tx_status); + printk_info("sis900_transmit: TX Timeout! Tx status %X.\n", tx_status); } if (tx_status & (ABORT | UNDERRUN | OWCOLL)) { /* packet unsuccessfully transmited */ - printk("sis900_transmit: Transmit error, Tx status %X.\n", tx_status); + printk_info("sis900_transmit: Transmit error, Tx status %X.\n", tx_status); } /* Disable interrupts by clearing the interrupt mask. */ outl(0, ioaddr + imr); @@ -1016,20 +1016,20 @@ sis900_poll(struct nic *nic) int retstat = 0; if (sis900_debug > 2) - printk("sis900_poll: cur_rx:%d, status:%X\n", cur_rx, rx_status); + printk_info("sis900_poll: cur_rx:%d, status:%X\n", cur_rx, rx_status); if (!(rx_status & OWN)) return retstat; if (sis900_debug > 1) - printk("sis900_poll: got a packet: cur_rx:%d, status:%X\n", + printk_info("sis900_poll: got a packet: cur_rx:%d, status:%X\n", cur_rx, rx_status); nic->packetlen = (rx_status & DSIZE) - CRC_SIZE; if (rx_status & (ABORT|OVERRUN|TOOLONG|RUNT|RXISERR|CRCERR|FAERR)) { /* corrupted packet received */ - printk("sis900_poll: Corrupted packet received, buffer status = %X\n", + printk_info("sis900_poll: Corrupted packet received, buffer status = %X\n", rx_status); retstat = 0; } else { diff --git a/src/include/cpu/p5/cpuid.h b/src/include/cpu/p5/cpuid.h index 511ae30f50..b8ffc88a84 100644 --- a/src/include/cpu/p5/cpuid.h +++ b/src/include/cpu/p5/cpuid.h @@ -1,25 +1,25 @@ -#ifndef _INTEL_CPUID_H_ -#define _INTEL_CPUID_H_ +#ifndef CPU_P5_CPUID_H +#define CPU_P5_CPUID_H -#ifdef i586 -int intel_mtrr_check(void); -#endif -void intel_display_cpuid(void); +int mtrr_check(void); +void display_cpuid(void); /* * Generic CPUID function. copied from Linux kernel headers */ -extern inline void intel_cpuid(int op, int *eax, int *ebx, int *ecx, int *edx) +static inline void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx) { - __asm__("cpuid" + __asm__("pushl %%ebx\n\t" + "cpuid\n\t" + "movl %%ebx, %%esi\n\t" + "popl %%ebx\n\t" : "=a" (*eax), - "=b" (*ebx), + "=S" (*ebx), "=c" (*ecx), "=d" (*edx) : "a" (op) : "cc"); } - -#endif /* _INTEL_CPUID_H_ */ +#endif /* CPU_P5_CPUID_H */ diff --git a/src/include/cpu/p6/l2_cache.h b/src/include/cpu/p6/l2_cache.h index 3390cdac18..9c8803d39d 100644 --- a/src/include/cpu/p6/l2_cache.h +++ b/src/include/cpu/p6/l2_cache.h @@ -15,4 +15,6 @@ #define BBL_CR_BUSY 0x11B #define BBL_CR_CTL3 0x11E +extern int p6_configure_l2_cache(void); + #endif /* __LINUXBIOS_P6_L2_CACHE_H */ diff --git a/src/include/cpu/p6/msr.h b/src/include/cpu/p6/msr.h index 1ed8ea8519..4977b0201d 100644 --- a/src/include/cpu/p6/msr.h +++ b/src/include/cpu/p6/msr.h @@ -1,3 +1,6 @@ +#ifndef CPU_P6_MSR_H +#define CPU_P6_MSR_H + /* * Access to machine-specific registers (available on 586 and better only) * Note: the rd* operations modify the parameters directly (without using @@ -27,4 +30,4 @@ __asm__ __volatile__("rdpmc" \ : "=a" (low), "=d" (high) \ : "c" (counter)) - +#endif /* CPU_P6_MSR_H */ diff --git a/src/include/cpu/p6/mtrr.h b/src/include/cpu/p6/mtrr.h index d8aeb85a60..c560e53872 100644 --- a/src/include/cpu/p6/mtrr.h +++ b/src/include/cpu/p6/mtrr.h @@ -1,5 +1,5 @@ -#ifndef __LINUXBIOS_MTRR_H -#define __LINUXBIOS_MTRR_H +#ifndef __LINUXBIOS_CPU_P6_MTRR_H +#define __LINUXBIOS_CPU_P6_MTRR_H /* These are the region types */ #define MTRR_TYPE_UNCACHABLE 0 @@ -30,4 +30,13 @@ #define MTRRfix4K_F0000_MSR 0x26e #define MTRRfix4K_F8000_MSR 0x26f -#endif /* __LINUXBIOS_MTRR_H */ + +#if !defined(ASSEMBLY) + +#if defined(INTEL_PPRO_MTRR) +void setup_mtrrs(unsigned long ramsizeK); +#endif + +#endif /* ASSEMBLY */ + +#endif /* __LINUXBIOS_CPU_P6_MTRR_H */ diff --git a/src/include/pci.h b/src/include/pci.h index 2fcd03e6ff..dd00adeaed 100644 --- a/src/include/pci.h +++ b/src/include/pci.h @@ -423,6 +423,7 @@ void pci_set_method(void); void pci_enumerate(void); void pci_configure(void); void pci_enable(void); +void pci_zero_irq_settings(void); // historical functions ... void intel_conf_writeb(unsigned long port, unsigned char value); diff --git a/src/include/printk.h b/src/include/printk.h index 0fe88f7897..8bddbfe402 100644 --- a/src/include/printk.h +++ b/src/include/printk.h @@ -1,27 +1,68 @@ #ifndef PRINTK_H #define PRINTK_H -/* These defines copied from linux/include/linux/kernel.h */ +#ifndef MAXIMUM_CONSOLE_LOGLEVEL +#define MAXIMUM_CONSOLE_LOGLEVEL 8 +#endif -#define KERN_EMERG "<0>" /* system is unusable */ -#define KERN_ALERT "<1>" /* action must be taken immediately */ -#define KERN_CRIT "<2>" /* critical conditions */ -#define KERN_ERR "<3>" /* error conditions */ -#define KERN_WARNING "<4>" /* warning conditions */ -#define KERN_NOTICE "<5>" /* normal but significant condition */ -#define KERN_INFO "<6>" /* informational */ -#define KERN_DEBUG "<7>" /* debug-level messages */ -#define KERN_SPEW "<8>" /* Way too many details */ +#define BIOS_EMERG 0 /* system is unusable */ +#define BIOS_ALERT 1 /* action must be taken immediately */ +#define BIOS_CRIT 2 /* critical conditions */ +#define BIOS_ERR 3 /* error conditions */ +#define BIOS_WARNING 4 /* warning conditions */ +#define BIOS_NOTICE 5 /* normal but significant condition */ +#define BIOS_INFO 6 /* informational */ +#define BIOS_DEBUG 7 /* debug-level messages */ +#define BIOS_SPEW 8 /* Way too many details */ extern int console_loglevel; -int printk(const char *fmt, ...); +int do_printk(int msg_level, const char *fmt, ...); -#ifdef DEBUG -#define DBG(x...) printk(KERN_DEBUG x) -#define PRINTK(x...) printk(x) -#else -#define DBG(x...) -#define PRINTK(x...) +#define printk_emerg(fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg) +#define printk_alart(fmt, arg...) do_printk(BIOS_ALERT ,fmt, ##arg) +#define printk_crit(fmt, arg...) do_printk(BIOS_CRIT ,fmt, ##arg) +#define printk_err(fmt, arg...) do_printk(BIOS_ERR ,fmt, ##arg) +#define printk_warning(fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg) +#define printk_notice(fmt, arg...) do_printk(BIOS_NOTICE ,fmt, ##arg) +#define printk_info(fmt, arg...) do_printk(BIOS_INFO ,fmt, ##arg) +#define printk_debug(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg) +#define printk_spew(fmt, arg...) do_printk(BIOS_SPEW ,fmt, ##arg) + +#if MAXIMUM_CONSOLE_LOGLEVEL <= 0 +#undef printk_emerg +#define printk_emerg(fmt, arg...) do {} while(0) +#endif +#if MAXIMUM_CONSOLE_LOGLEVEL <= 1 +#undef printk_alert +#define printk_alart(fmt, arg...) do {} while(0) +#endif +#if MAXIMUM_CONSOLE_LOGLEVEL <= 2 +#undef printk_crit +#define printk_crit(fmt, arg...) do {} while(0) +#endif +#if MAXIMUM_CONSOLE_LOGLEVEL <= 3 +#undef printk_err +#define printk_err(fmt, arg...) do {} while(0) +#endif +#if MAXIMUM_CONSOLE_LOGLEVEL <= 4 +#undef printk_warning +#define printk_warning(fmt, arg...) do {} while(0) +#endif +#if MAXIMUM_CONSOLE_LOGLEVEL <= 5 +#undef printk_notice +#define printk_notice(fmt, arg...) do {} while(0) +#endif +#if MAXIMUM_CONSOLE_LOGLEVEL <= 6 +#undef printk_info +#define printk_info(fmt, arg...) do {} while(0) +#endif +#if MAXIMUM_CONSOLE_LOGLEVEL <= 7 +#undef printk_debug +#define printk_debug(fmt, arg...) do {} while(0) +#endif +#if MAXIMUM_CONSOLE_LOGLEVEL <= 8 +#undef printk_spew +#define printk_spew(fmt, arg...) do {} while(0) #endif #endif diff --git a/src/include/serial_subr.h b/src/include/serial_subr.h index da543b6a87..0083bb692f 100644 --- a/src/include/serial_subr.h +++ b/src/include/serial_subr.h @@ -3,5 +3,8 @@ void ttys0_init(void); void ttys0_tx_byte(unsigned char data); +unsigned char ttys0_rx_byte(void); +unsigned long ttys0_rx_bytes(char *buffer, unsigned long size); +void uart_init(unsigned base_port, unsigned divisor); #endif /* _SERIAL_SUBR_H_ */ diff --git a/src/lib/Config b/src/lib/Config index 1e308396cd..d53b1dc473 100644 --- a/src/lib/Config +++ b/src/lib/Config @@ -11,4 +11,5 @@ object memcmp.o object malloc.o object elfboot.o object do_inflate.o +object delay.o diff --git a/src/lib/do_inflate.c b/src/lib/do_inflate.c index 8f1c76545f..1cbc810ca2 100644 --- a/src/lib/do_inflate.c +++ b/src/lib/do_inflate.c @@ -41,11 +41,11 @@ typedef unsigned long ulg; #ifdef TRACEV -# define Trace(x) printk(KERN_DDEBUG x) -# define Tracev(x) {if (verbose) printk(KERN_DDEBUG x);} -# define Tracevv(x) {if (verbose>1) printk(KERN_DDEBUG x);} -# define Tracec(c,x) {if (verbose && (c)) printk(KERN_DDEBUG x);} -# define Tracecv(c,x) {if (verbose>1 && (c)) printk(KERN_DDEBUG x);} +# define Trace(x) printk_debug(x) +# define Tracev(x) {if (verbose) printk_debug(x);} +# define Tracevv(x) {if (verbose>1) printk_debug(x);} +# define Tracec(c,x) {if (verbose && (c)) printk_debug(x);} +# define Tracecv(c,x) {if (verbose>1 && (c)) printk_debug(x);} #else # define Trace(x) # define Tracev(x) @@ -73,7 +73,7 @@ static void flush_window(void) in = window; out = &output_data[output_ptr]; - DBG("flush 0x%08x count 0x%08x\n", (unsigned long) out, outcnt); + printk_debug("flush 0x%08x count 0x%08x\n", (unsigned long) out, outcnt); for (n = 0; n < outcnt; n++) { ch = *out++ = *in++; @@ -96,6 +96,6 @@ void gunzip_setup(void) window = malloc(WSIZE); #endif output_data = (char *) KERNEL_START; - DBG("output data is 0x%08x\n", (unsigned long) output_data); + printk_debug("output data is 0x%08x\n", (unsigned long) output_data); makecrc(); } diff --git a/src/lib/elfboot.c b/src/lib/elfboot.c index e18c0d39b2..a0cb544be4 100644 --- a/src/lib/elfboot.c +++ b/src/lib/elfboot.c @@ -57,11 +57,11 @@ int elfboot(size_t totalram) void *ptr, *entry; int i; - printk("\n"); - printk("Welcome to elfboot, the open sourced starter.\n"); - printk("Febuary 2001, Eric Biederman.\n"); - printk("Version 0.99\n"); - printk("\n"); + printk_info("\n"); + printk_info("Welcome to elfboot, the open sourced starter.\n"); + printk_info("Febuary 2001, Eric Biederman.\n"); + printk_info("Version 0.99\n"); + printk_info("\n"); ptr = get_ube_pointer(totalram); post_code(0xf8); @@ -88,11 +88,10 @@ int elfboot(size_t totalram) /* Sanity check the segments and zero the extra bytes */ for(i = 0; i < ehdr->e_phnum; i++) { - unsigned long start; unsigned char *dest, *end; if (!safe_range(phdr[i].p_paddr, phdr[i].p_memsz)) { - printk("Bad memory range: [0x%016lx, 0x%016lx)\n", + printk_err("Bad memory range: [0x%016lx, 0x%016lx)\n", phdr[i].p_paddr, phdr[i].p_memsz); goto out; } @@ -100,9 +99,14 @@ int elfboot(size_t totalram) end = dest + phdr[i].p_memsz; dest += phdr[i].p_filesz; - /* Zero the extra bytes */ - while(dest < end) { - *(dest++) = 0; + if (dest < end) { + printk_debug("Clearing Section: addr: 0x%016lx memsz: 0x%016lx\n", + (unsigned long)dest, end - dest); + + /* Zero the extra bytes */ + while(dest < end) { + *(dest++) = 0; + } } } @@ -137,7 +141,7 @@ int elfboot(size_t totalram) if (!cur_phdr) { break; } - printk("Loading Section: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", + printk_debug("Loading Section: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", cur_phdr->p_paddr, cur_phdr->p_memsz, cur_phdr->p_filesz); /* Compute the boundaries of the section */ @@ -186,21 +190,21 @@ int elfboot(size_t totalram) /* The extra bytes between dest & end have been zeroed */ } - DBG("Jumping to boot code\n"); + printk_debug("Jumping to boot code\n"); post_code(0xfe); /* Jump to kernel */ jmp_to_elf_entry(entry, ptr); out: - printk("Bad ELF Image\n"); + printk_err("Bad ELF Image\n"); for(i = 0; i < sizeof(*ehdr); i++) { if ((i & 0xf) == 0) { - printk("\n"); + printk_err("\n"); } - printk("%02x ", header[i]); + printk_err("%02x ", header[i]); } - printk("\n"); + printk_err("\n"); return 0; } diff --git a/src/lib/inflate.c b/src/lib/inflate.c index 337de31df4..99e796e8c0 100644 --- a/src/lib/inflate.c +++ b/src/lib/inflate.c @@ -999,7 +999,7 @@ STATIC int inflate() /* return success */ - DBG("<%u> ", h); + printk_debug("<%u> ", h); return 0; } diff --git a/src/lib/linuxbiosmain.c b/src/lib/linuxbiosmain.c index 82b0c37ce9..5c8102be6b 100644 --- a/src/lib/linuxbiosmain.c +++ b/src/lib/linuxbiosmain.c @@ -52,13 +52,13 @@ int linuxbiosmain(unsigned long base, unsigned long totalram) #if USE_ELF_BOOT return elfboot(totalram); #else /* !ELF_BOOT */ - printk("\n"); - printk("Welcome to start32, the open sourced starter.\n"); - printk("This space will eventually hold more diagnostic information.\n"); - printk("\n"); - printk("January 2000, James Hendricks, Dale Webster, and Ron Minnich.\n"); - printk("Version 0.1\n"); - printk("\n"); + printk_info("\n"); + printk_info("Welcome to start32, the open sourced starter.\n"); + printk_info("This space will eventually hold more diagnostic information.\n"); + printk_info("\n"); + printk_info("January 2000, James Hendricks, Dale Webster, and Ron Minnich.\n"); + printk_info("Version 0.1\n"); + printk_info("\n"); initrd_start = 0; initrd_size = 0; @@ -82,44 +82,44 @@ int linuxbiosmain(unsigned long base, unsigned long totalram) post_code(0xf1); #ifdef PYRO_TEST1 - printk(KERN_NOTICE "LiLa loader, press a key to test netboot_init:"); + printk_notice( "LiLa loader, press a key to test netboot_init:"); buflen = sizeof(buffer); ttys0_rx_line(buffer, &buflen); #endif #ifdef USE_TFTP netboot_init(); - printk(KERN_NOTICE "\nnetboot_init test complete, all is well (I hope!)\n"); + printk_notice("\nnetboot_init test complete, all is well (I hope!)\n"); #endif /* USE_TFTP */ - DBG("Gunzip setup\n"); + printk_debug("Gunzip setup\n"); gunzip_setup(); - DBG("Gunzipping boot code\n"); + printk_debug("Gunzipping boot code\n"); if (gunzip() != 0) { - printk("gunzip failed\n"); + printk_notice("gunzip failed\n"); post_code(0xff); return 0; } post_code(0xf8); #ifdef TFTP_INITRD - printk("Loading initrd now\n"); + printk_notice("Loading initrd now\n"); buflen = tftp_init("initrd"); - printk("TFTP init complete (%d)\n",buflen); + printk_notice("TFTP init complete (%d)\n",buflen); buflen = 512; // I know, not it's purpose, // but it isn't being used at this point. bufptr = (char *) initrd_start = 0x0400000; while (buflen == 512) { buflen = tftp_fetchone(bufptr); #ifdef DEBUG_TFTP - printk("Got block, bufptr = %lu, size= %u\n",bufptr, buflen); + printk_spew("Got block, bufptr = %lu, size= %u\n",bufptr, buflen); #endif bufptr += buflen; } initrd_size = (unsigned long) bufptr - initrd_start; - printk("Initrd loaded\n"); + printk_notice("Initrd loaded\n"); if(tftp_init("cmdline") >=0) { buflen = tftp_fetchone(buffer); @@ -127,7 +127,7 @@ int linuxbiosmain(unsigned long base, unsigned long totalram) cmd_line=buffer; } - printk("Booting with command line: %s\n",cmd_line); + printk_notice("Booting with command line: %s\n",cmd_line); #endif /* TFTP_INITRD */ @@ -149,7 +149,7 @@ int linuxbiosmain(unsigned long base, unsigned long totalram) set_memory_size(empty_zero_page, 0x3c00, totalram - 2048); post_code(0xfa); - PRINTK(KERN_NOTICE "command line - [%s]\n", cmd_line); + printk_notice("command line - [%s]\n", cmd_line); set_command_line(empty_zero_page, cmd_line); set_root_rdonly(empty_zero_page); @@ -157,7 +157,7 @@ int linuxbiosmain(unsigned long base, unsigned long totalram) set_initrd(empty_zero_page, initrd_start, initrd_size); - DBG("Jumping to boot code\n"); + printk_debug("Jumping to boot code\n"); post_code(0xfe); /* there seems to be a bug in gas? it's generating wrong bit-patterns ... diff --git a/src/lib/linuxpci.c b/src/lib/linuxpci.c index 3e5987291e..1f257b9120 100644 --- a/src/lib/linuxpci.c +++ b/src/lib/linuxpci.c @@ -22,12 +22,6 @@ static char rcsid[] = "$Id$"; #include -#undef DEBUGSCAN -#ifdef DEBUGSCAN -#define DBGSCAN(x...) printk(KERN_DEBUG x) -#else -#define DBGSCAN(x...) -#endif /** * This is the root of the PCI tree. A PCI tree always has @@ -104,14 +98,14 @@ void pci_set_master(struct pci_dev *dev) pci_read_config_word(dev, PCI_COMMAND, &cmd); if (!(cmd & PCI_COMMAND_MASTER)) { - DBG("PCI: Enabling bus mastering for device %02x:%02x\n", + printk_debug("PCI: Enabling bus mastering for device %02x:%02x\n", dev->bus->number, dev->devfn); cmd |= PCI_COMMAND_MASTER; pci_write_config_word(dev, PCI_COMMAND, cmd); } pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); if (lat < 16) { - DBG("PCI: Increasing latency timer of device %02x:%02x to 64\n", + printk_debug("PCI: Increasing latency timer of device %02x:%02x to 64\n", dev->bus->number, dev->devfn); pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); } @@ -173,7 +167,7 @@ void pci_read_bases(struct pci_dev *dev, unsigned int howmany) addr &= (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK); if (addr == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) { - DBG("reg %d is 64-bit\n", reg); + printk_debug("reg %d is 64-bit\n", reg); /* this is a 64-bit memory base address */ reg++; pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (reg << 2), &addr); @@ -181,7 +175,7 @@ void pci_read_bases(struct pci_dev *dev, unsigned int howmany) #if BITS_PER_LONG == 64 dev->base_address[reg - 1] |= ((unsigned long) addr) << 32; #else - printk(KERN_ERR "PCI: Unable to handle 64-bit address for device " + printk_err("PCI: Unable to handle 64-bit address for device " "%02x:%02x\n", dev->bus->number, dev->devfn); dev->base_address[reg - 1] = 0; #endif @@ -200,7 +194,7 @@ unsigned int pci_scan_bus(struct pci_bus *bus) struct pci_dev *dev, **bus_last; struct pci_bus *child; - DBG("PCI: pci_scan_bus for bus %d\n", bus->number); + printk_debug("PCI: pci_scan_bus for bus %d\n", bus->number); bus_last = &bus->devices; max = bus->secondary; @@ -210,14 +204,14 @@ unsigned int pci_scan_bus(struct pci_bus *bus) /* probe all devices on this bus with some optimization for non-existance and single funcion devices */ for (devfn = 0; devfn < 0xff; devfn++) { - u32 id, class, addr; + u32 id, class, addr; u8 cmd, tmp, hdr_type; // gcc just went to hell. Don't test -- this always // returns 0 anyway. #if GCC_WORKS_ON_O2 if (pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID, &id)) { - DBGSCAN("PCI: devfn 0x%x, read_config_dword fails\n", + printk_spew("PCI: devfn 0x%x, read_config_dword fails\n", devfn); continue; } @@ -226,7 +220,7 @@ unsigned int pci_scan_bus(struct pci_bus *bus) /* some broken boards return 0 if a slot is empty: */ if (id == 0xffffffff || id == 0x00000000 || id == 0x0000ffff || id == 0xffff0000) { - DBGSCAN("PCI: devfn 0x%x, bad id 0x%x\n", devfn, id); + printk_spew("PCI: devfn 0x%x, bad id 0x%x\n", devfn, id); if (PCI_FUNC(devfn) == 0x00) { /* if this is a function 0 device and it is not present, skip to next device */ @@ -237,17 +231,17 @@ unsigned int pci_scan_bus(struct pci_bus *bus) } if (pcibios_read_config_byte(bus->number, devfn, PCI_HEADER_TYPE, &hdr_type)){ - DBGSCAN("PCI: devfn 0x%x, header type read fails\n", devfn); + printk_spew("PCI: devfn 0x%x, header type read fails\n", devfn); continue; } if (pcibios_read_config_dword(bus->number, devfn, PCI_CLASS_REVISION, &class)) { - DBGSCAN("PCI: devfn 0x%x, class read fails\n", devfn); + printk_spew("PCI: devfn 0x%x, class read fails\n", devfn); continue; } if ((dev = kmalloc(sizeof(*dev), GFP_ATOMIC)) == 0) { - printk(KERN_ERR "PCI: out of memory.\n"); + printk_err("PCI: out of memory.\n"); continue; } @@ -292,14 +286,14 @@ unsigned int pci_scan_bus(struct pci_bus *bus) break; default: /* unknown header */ bad: - printk(KERN_ERR "PCI: %02x:%02x [%04x/%04x/%06x] has unknown header " + printk_err("PCI: %02x:%02x [%04x/%04x/%06x] has unknown header " "type %02x, ignoring.\n", bus->number, dev->devfn, dev->vendor, dev->device, class, hdr_type); continue; } - DBG("PCI: %02x:%02x [%04x/%04x]\n", bus->number, dev->devfn, + printk_debug("PCI: %02x:%02x [%04x/%04x]\n", bus->number, dev->devfn, dev->vendor, dev->device); /* Put it into the global PCI device chain. It's used to find devices once @@ -374,7 +368,7 @@ unsigned int pci_scan_bus(struct pci_bus *bus) #endif /* Insert it into the tree of buses. */ if ((child = kmalloc(sizeof(*child), GFP_ATOMIC)) == 0) { - printk(KERN_ERR "PCI: out of memory for bridge.\n"); + printk_err("PCI: out of memory for bridge.\n"); continue; } memset(child, 0, sizeof(*child)); @@ -454,7 +448,7 @@ unsigned int pci_scan_bus(struct pci_bus *bus) * * Return how far we've got finding sub-buses. */ - DBG("PCI: pci_scan_bus returning with max=%02x\n", max); + printk_debug("PCI: pci_scan_bus returning with max=%02x\n", max); post_code(0x55); return max; } diff --git a/src/lib/malloc.c b/src/lib/malloc.c index e954e3889c..f5b164c1e9 100644 --- a/src/lib/malloc.c +++ b/src/lib/malloc.c @@ -5,7 +5,7 @@ #if 1 #define MALLOCDBG(x) #else -#define MALLOCDBG(x) printk x +#define MALLOCDBG(x) printk_spew x #endif extern unsigned char _heap, _eheap; static size_t free_mem_ptr = (size_t)&_heap; /* Start of heap */ @@ -15,13 +15,13 @@ static size_t free_mem_end_ptr = (size_t)&_eheap; /* End of heap */ void malloc_mark(malloc_mark_t *place) { *place = free_mem_ptr; - DBG("malloc_mark 0x%08lx\n", (unsigned long)free_mem_ptr); + printk_spew("malloc_mark 0x%08lx\n", (unsigned long)free_mem_ptr); } void malloc_release(malloc_mark_t *ptr) { free_mem_ptr = *ptr; - DBG("malloc_release 0x%08lx\n", (unsigned long)free_mem_ptr); + printk_spew("malloc_release 0x%08lx\n", (unsigned long)free_mem_ptr); } void *malloc(size_t size) diff --git a/src/lib/newpci.c b/src/lib/newpci.c index 5cdc94d11e..5ad9862b10 100644 --- a/src/lib/newpci.c +++ b/src/lib/newpci.c @@ -221,7 +221,7 @@ static int pci_sanity_check(const struct pci_ops *o) (!o->read_word(bus, devfn, PCI_VENDOR_ID, &x) && (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ))) return 1; - printk(KERN_ERR "PCI: Sanity check failed\n"); + printk_err("PCI: Sanity check failed\n"); return 0; } @@ -239,7 +239,7 @@ static const struct pci_ops *pci_check_direct(void) if (inl(0xCF8) == 0x80000000 && pci_sanity_check(&pci_direct_conf1)) { outl(tmp, 0xCF8); - printk(KERN_INFO "PCI: Using configuration type 1\n"); + printk_debug("PCI: Using configuration type 1\n"); return &pci_direct_conf1; } outl(tmp, 0xCF8); @@ -254,7 +254,7 @@ static const struct pci_ops *pci_check_direct(void) outb(0x00, 0xCFA); if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00 && pci_sanity_check(&pci_direct_conf2)) { - printk(KERN_INFO "PCI: Using configuration type 2\n"); + printk_debug("PCI: Using configuration type 2\n"); return &pci_direct_conf2; } } @@ -267,7 +267,7 @@ int pci_read_config_byte(struct pci_dev *dev, u8 where, u8 * val) { int res; res = conf->read_byte(dev->bus->number, dev->devfn, where, val); - PRINTK(KERN_SPEW "Read config byte bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n", + printk_spew("Read config byte bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n", dev->bus->number, dev->devfn, where, *val, res); return res; @@ -278,7 +278,7 @@ int pci_read_config_word(struct pci_dev *dev, u8 where, u16 * val) { int res; res = conf->read_word(dev->bus->number, dev->devfn, where, val); - PRINTK(KERN_SPEW "Read config word bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n", + printk_spew( "Read config word bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n", dev->bus->number, dev->devfn, where, *val, res); return res; } @@ -287,21 +287,21 @@ int pci_read_config_dword(struct pci_dev *dev, u8 where, u32 * val) { int res; res = conf->read_dword(dev->bus->number, dev->devfn, where, val); - PRINTK(KERN_SPEW "Read config dword bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n", + printk_spew( "Read config dword bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n", dev->bus->number, dev->devfn, where, *val, res); return res; } int pci_write_config_byte(struct pci_dev *dev, u8 where, u8 val) { - PRINTK(KERN_SPEW "Write config byte bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n", + printk_spew( "Write config byte bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n", dev->bus->number, dev->devfn, where, val); return conf->write_byte(dev->bus->number, dev->devfn, where, val); } int pci_write_config_word(struct pci_dev *dev, u8 where, u16 val) { - PRINTK(KERN_SPEW "Write config word bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n", + printk_spew( "Write config word bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n", dev->bus->number, dev->devfn, where, val); return conf->write_word(dev->bus->number, dev->devfn, where, val); @@ -309,7 +309,7 @@ int pci_write_config_word(struct pci_dev *dev, u8 where, u16 val) int pci_write_config_dword(struct pci_dev *dev, u8 where, u32 val) { - PRINTK(KERN_SPEW "Write config dword bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n", + printk_spew( "Write config dword bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n", dev->bus->number, dev->devfn, where, val); return conf->write_dword(dev->bus->number, dev->devfn, where, val); } @@ -318,7 +318,7 @@ int pcibios_read_config_byte(unsigned char bus, unsigned char devfn, u8 where, u { int res; res = conf->read_byte(bus, devfn, where, val); - PRINTK(KERN_SPEW "Read config byte bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n", + printk_spew( "Read config byte bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n", bus, devfn, where, *val, res); return res; } @@ -327,7 +327,7 @@ int pcibios_read_config_word(unsigned char bus, unsigned char devfn, u8 where, u { int res; res = conf->read_word(bus, devfn, where, val); - PRINTK(KERN_SPEW "Read config word bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n", + printk_spew( "Read config word bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n", bus, devfn, where, *val, res); return res; @@ -337,7 +337,7 @@ int pcibios_read_config_dword(unsigned char bus, unsigned char devfn, u8 where, { int res; res = conf->read_dword(bus, devfn, where, val); - PRINTK(KERN_SPEW "Read config dword bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n", + printk_spew( "Read config dword bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n", bus, devfn, where, *val, res); return res; @@ -345,7 +345,7 @@ int pcibios_read_config_dword(unsigned char bus, unsigned char devfn, u8 where, int pcibios_write_config_byte(unsigned char bus, unsigned char devfn, u8 where, u8 val) { - PRINTK(KERN_SPEW "Write byte bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n", + printk_spew( "Write byte bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n", bus, devfn, where, val); return conf->write_byte(bus, devfn, where, val); @@ -353,7 +353,7 @@ int pcibios_write_config_byte(unsigned char bus, unsigned char devfn, u8 where, int pcibios_write_config_word(unsigned char bus, unsigned char devfn, u8 where, u16 val) { - PRINTK(KERN_SPEW "Write word bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n", + printk_spew( "Write word bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n", bus, devfn, where, val); return conf->write_word(bus, devfn, where, val); @@ -361,7 +361,7 @@ int pcibios_write_config_word(unsigned char bus, unsigned char devfn, u8 where, int pcibios_write_config_dword(unsigned char bus, unsigned char devfn, u8 where, u32 val) { - PRINTK(KERN_SPEW "Write doubleword bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n", + printk_spew( "Write doubleword bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n", bus, devfn, where, val); return conf->write_dword(bus, devfn, where, val); } @@ -449,7 +449,7 @@ void compute_allocate_io(struct pci_bus *bus) unsigned long io_base; io_base = bus->iobase; - PRINTK(KERN_DEBUG"compute_allocate_io: base 0x%lx\n", bus->iobase); + printk_debug("compute_allocate_io: base 0x%lx\n", bus->iobase); /* First, walk all the bridges. When you return, grow the limit of the current bus since sub-busses need IO rounded to 4096 */ @@ -457,7 +457,7 @@ void compute_allocate_io(struct pci_bus *bus) curbus->iobase = io_base; compute_allocate_io(curbus); io_base = round(curbus->iolimit, IO_BRIDGE_ALIGN); - PRINTK(KERN_DEBUG"BUSIO: done Bridge Bus 0x%x, iobase now 0x%lx\n", + printk_debug("BUSIO: done Bridge Bus 0x%x, iobase now 0x%lx\n", curbus->number, io_base); } @@ -470,7 +470,7 @@ void compute_allocate_io(struct pci_bus *bus) if (!iosize) continue; - PRINTK(KERN_DEBUG"DEVIO: Bus 0x%x, devfn 0x%x, reg 0x%x: " + printk_debug("DEVIO: Bus 0x%x, devfn 0x%x, reg 0x%x: " "iosize 0x%lx\n", curdev->bus->number, curdev->devfn, i, iosize); curdev->base_address[i] = io_base; @@ -478,7 +478,7 @@ void compute_allocate_io(struct pci_bus *bus) // (e.g. VIA 82c686a.) So set it to be safe) curdev->base_address[i] |= PCI_BASE_ADDRESS_SPACE_IO; - PRINTK(KERN_DEBUG"-->set base to 0x%lx\n", io_base); + printk_debug("-->set base to 0x%lx\n", io_base); io_base += round(iosize, IO_ALIGN); curdev->command |= PCI_COMMAND_IO; } @@ -486,7 +486,7 @@ void compute_allocate_io(struct pci_bus *bus) } bus->iolimit = iolimit(io_base); - PRINTK(KERN_DEBUG"BUS %d: set iolimit to 0x%lx\n", bus->number, bus->iolimit); + printk_debug("BUS %d: set iolimit to 0x%lx\n", bus->number, bus->iolimit); } /** Compute and allocate the memory for this bus. @@ -500,7 +500,7 @@ void compute_allocate_mem(struct pci_bus *bus) unsigned long mem_base; mem_base = bus->membase; - PRINTK(KERN_DEBUG"compute_allocate_mem: base 0x%lx\n", bus->membase); + printk_debug("compute_allocate_mem: base 0x%lx\n", bus->membase); /* First, walk all the bridges. When you return, grow the limit of the current bus since sub-busses need MEMORY rounded to 1 Mega */ @@ -508,7 +508,7 @@ void compute_allocate_mem(struct pci_bus *bus) curbus->membase = mem_base; compute_allocate_mem(curbus); mem_base = round(curbus->memlimit, ONEMEG); - PRINTK(KERN_DEBUG"BUSMEM: Bridge Bus 0x%x,membase now 0x%lx\n", + printk_debug("BUSMEM: Bridge Bus 0x%x,membase now 0x%lx\n", curbus->number, mem_base); } @@ -549,11 +549,11 @@ void compute_allocate_mem(struct pci_bus *bus) consumed in 4KB unit */ regmem = round(memorysize, MEM_ALIGN); mem_base = round(mem_base, regmem); - PRINTK(KERN_DEBUG"DEVMEM: Bus 0x%x, devfn 0x%x, reg 0x%x: " + printk_debug("DEVMEM: Bus 0x%x, devfn 0x%x, reg 0x%x: " "memsize 0x%lx\n", curdev->bus->number, curdev->devfn, i, regmem); curdev->base_address[i] = mem_base; - PRINTK(KERN_DEBUG"-->set base to 0x%lx\n", mem_base); + printk_debug("-->set base to 0x%lx\n", mem_base); mem_base += regmem; curdev->command |= PCI_COMMAND_MEMORY; // for 64-bit BARs, the odd ones don't count @@ -565,7 +565,7 @@ void compute_allocate_mem(struct pci_bus *bus) } bus->memlimit = memlimit(mem_base); - PRINTK(KERN_DEBUG"BUS %d: set memlimit to 0x%lx\n", bus->number, bus->memlimit); + printk_debug("BUS %d: set memlimit to 0x%lx\n", bus->number, bus->memlimit); } /** Compute and allocate the prefetch memory for this bus. @@ -579,7 +579,7 @@ void compute_allocate_prefmem(struct pci_bus *bus) unsigned long prefmem_base; prefmem_base = bus->prefmembase; - PRINTK(KERN_DEBUG"Compute_allocate_prefmem: base 0x%lx\n", bus->prefmembase); + printk_debug("Compute_allocate_prefmem: base 0x%lx\n", bus->prefmembase); /* First, walk all the bridges. When you return, grow the limit of the current bus since sub-busses need MEMORY rounded to 1 Mega */ @@ -587,7 +587,7 @@ void compute_allocate_prefmem(struct pci_bus *bus) curbus->prefmembase = prefmem_base; compute_allocate_prefmem(curbus); prefmem_base = round(curbus->prefmemlimit, ONEMEG); - PRINTK(KERN_DEBUG"BUSPREFMEM: Bridge Bus 0x%x, prefmem base now 0x%lx\n", + printk_debug("BUSPREFMEM: Bridge Bus 0x%x, prefmem base now 0x%lx\n", curbus->number, prefmem_base); } @@ -607,7 +607,7 @@ void compute_allocate_prefmem(struct pci_bus *bus) // we don't support the 1M type if (type & PCI_BASE_ADDRESS_MEM_TYPE_1M) { - printk(__FUNCTION__ ": 1M memory not supported\n"); + printk_warning(__FUNCTION__ ": 1M memory not supported\n"); continue; } @@ -627,11 +627,11 @@ void compute_allocate_prefmem(struct pci_bus *bus) consumed in 4KB unit */ regmem = round(memorysize, MEM_ALIGN); prefmem_base = round(prefmem_base, regmem); - PRINTK(KERN_DEBUG"DEVPREFMEM: Bus 0x%x, devfn 0x%x, reg 0x%x: " + printk_debug("DEVPREFMEM: Bus 0x%x, devfn 0x%x, reg 0x%x: " "prefmemsize 0x%lx\n", curdev->bus->number, curdev->devfn, i, regmem); curdev->base_address[i] = prefmem_base; - PRINTK(KERN_DEBUG"-->set base to 0x%lx\n", prefmem_base); + printk_debug("-->set base to 0x%lx\n", prefmem_base); prefmem_base += regmem; curdev->command |= PCI_COMMAND_MEMORY; // for 64-bit BARs, the odd ones don't count @@ -642,7 +642,7 @@ void compute_allocate_prefmem(struct pci_bus *bus) } bus->prefmemlimit = memlimit(prefmem_base); - PRINTK(KERN_DEBUG"BUS %d: set prefmemlimit to 0x%lx\n", bus->number, bus->prefmemlimit); + printk_debug("BUS %d: set prefmemlimit to 0x%lx\n", bus->number, bus->prefmemlimit); } /** Compute and allocate resources. @@ -653,16 +653,16 @@ void compute_allocate_prefmem(struct pci_bus *bus) */ void compute_allocate_resources(struct pci_bus *bus) { - PRINTK(KERN_DEBUG"COMPUTE_ALLOCATE: do IO\n"); + printk_debug("COMPUTE_ALLOCATE: do IO\n"); compute_allocate_io(bus); - PRINTK(KERN_DEBUG"COMPUTE_ALLOCATE: do MEM\n"); + printk_debug("COMPUTE_ALLOCATE: do MEM\n"); compute_allocate_mem(bus); // now put the prefetchable memory at the end of the memory bus->prefmembase = round(bus->memlimit, ONEMEG); - PRINTK(KERN_DEBUG"COMPUTE_ALLOCATE: do PREFMEM\n"); + printk_debug("COMPUTE_ALLOCATE: do PREFMEM\n"); compute_allocate_prefmem(bus); } @@ -676,9 +676,9 @@ void assign_resources(struct pci_bus *bus) struct pci_dev *curdev = pci_devices; struct pci_bus *curbus; - PRINTK(KERN_DEBUG"ASSIGN RESOURCES, bus %d\n", bus->number); + printk_debug("ASSIGN RESOURCES, bus %d\n", bus->number); - /* wlak trhough all the buses, assign resources for bridges */ + /* walk trhough all the buses, assign resources for bridges */ for (curbus = bus->children; curbus; curbus = curbus->next) { curbus->self->command = 0; @@ -690,7 +690,7 @@ void assign_resources(struct pci_bus *bus) curbus->iobase >> 8); pci_write_config_byte(curbus->self, PCI_IO_LIMIT, curbus->iolimit >> 8); - PRINTK(KERN_DEBUG"Bus 0x%x iobase to 0x%x iolimit 0x%x\n", + printk_debug("Bus 0x%x iobase to 0x%x iolimit 0x%x\n", bus->number, curbus->iobase, curbus->iolimit); } @@ -701,7 +701,7 @@ void assign_resources(struct pci_bus *bus) curbus->membase >> 16); pci_write_config_word(curbus->self, PCI_MEMORY_LIMIT, curbus->memlimit >> 16); - PRINTK(KERN_DEBUG"Bus 0x%x membase to 0x%x memlimit 0x%x\n", + printk_debug("Bus 0x%x membase to 0x%x memlimit 0x%x\n", bus->number, curbus->membase, curbus->memlimit); } @@ -713,11 +713,12 @@ void assign_resources(struct pci_bus *bus) curbus->prefmembase >> 16); pci_write_config_word(curbus->self, PCI_PREF_MEMORY_LIMIT, curbus->prefmemlimit >> 16); - PRINTK(KERN_DEBUG"Bus 0x%x prefmembase to 0x%x prefmemlimit 0x%x\n", + printk_debug("Bus 0x%x prefmembase to 0x%x prefmemlimit 0x%x\n", bus->number, curbus->prefmembase, curbus->prefmemlimit); } curbus->self->command |= PCI_COMMAND_MASTER; + } for (curdev = pci_devices; curdev; curdev = curdev->next) { @@ -729,10 +730,12 @@ void assign_resources(struct pci_bus *bus) reg = PCI_BASE_ADDRESS_0 + (i << 2); pci_write_config_dword(curdev, reg, curdev->base_address[i]); - PRINTK(KERN_DEBUG"Bus 0x%x devfn 0x%x reg 0x%x base to 0x%lx\n", + printk_debug("Bus 0x%x devfn 0x%x reg 0x%x base to 0x%lx\n", curdev->bus->number, curdev->devfn, i, curdev->base_address[i]); } + /* set a default latency timer */ + pci_write_config_byte(curdev, PCI_LATENCY_TIMER, 0x40); } } @@ -748,7 +751,7 @@ void enable_resources(struct pci_bus *bus) pci_read_config_word(curdev, PCI_COMMAND, &command); command |= curdev->command; pci_write_config_word(curdev, PCI_COMMAND, command); - PRINTK(KERN_DEBUG"DEV Set command bus 0x%x devfn 0x%x to 0x%x\n", + printk_debug("DEV Set command bus 0x%x devfn 0x%x to 0x%x\n", curdev->bus->number, curdev->devfn, command); } } @@ -757,8 +760,10 @@ void enable_resources(struct pci_bus *bus) */ void pci_enumerate() { + printk_info("Scanning PCI bus..."); // scan it. pci_init(); + printk_info("done\n"); } /** Starting at the root, compute what resources are needed and allocate them. @@ -768,6 +773,7 @@ void pci_enumerate() */ void pci_configure() { + printk_info("Allocating PCI resources..."); pci_root.membase = PCI_MEM_START; pci_root.prefmembase = PCI_MEM_START; pci_root.iobase = PCI_IO_START; @@ -775,6 +781,7 @@ void pci_configure() compute_allocate_resources(&pci_root); // now just set things into registers ... we hope ... assign_resources(&pci_root); + printk_info("done.\n"); } /** Starting at the root, walk the tree and enable all devices/bridges. @@ -782,49 +789,71 @@ void pci_configure() */ void pci_enable() { + printk_info("Enabling PCI resourcess..."); + // now enable everything. enable_resources(&pci_root); + printk_info("done.\n"); +} + +void pci_zero_irq_settings(void) +{ + struct pci_dev *pcidev; + unsigned char line; + + printk_info("Zeroing PCI IRQ settings..."); + + pcidev = pci_devices; + + while (pcidev) { + pci_read_config_byte(pcidev, 0x3d, &line); + if (line) { + pci_write_config_byte(pcidev, 0x3c, 0); + } + pcidev = pcidev->next; + } + printk_info("done.\n"); } void handle_superio(int pass, struct superio *s, int nsuperio) { int i; - printk(KERN_INFO "handle_superio start, s %p nsuperio %d s->super %p\n", + printk_debug("handle_superio start, s %p nsuperio %d s->super %p\n", s, nsuperio, s->super); for(i = 0; i < nsuperio; i++, s++){ if (!s->super) continue; - printk(KERN_INFO "handle_superio: Pass %d, Superio %s\n", pass, + printk_debug("handle_superio: Pass %d, Superio %s\n", pass, s->super->name); // if no port is assigned use the defaultport - printk(KERN_INFO __FUNCTION__ " port 0x%x, defaultport 0x%x\n", + printk_info( __FUNCTION__ " port 0x%x, defaultport 0x%x\n", s->port, s->super->defaultport); if (! s->port) s->port = s->super->defaultport; - printk(KERN_INFO __FUNCTION__ " Using port 0x%x\n", s->port); + printk_info( __FUNCTION__ " Using port 0x%x\n", s->port); // need to have both pre_pci_init and devfn defined. if (s->super->pre_pci_init && (pass == 0)) { - printk(KERN_INFO " Call pre_pci_init\n"); + printk_debug(" Call pre_pci_init\n"); s->super->pre_pci_init(s); } else if (s->super->init && (pass == 1)) { - printk(KERN_INFO " Call init\n"); + printk_debug(" Call init\n"); s->super->init(s); } else if (s->super->finishup && (pass == 2)) { - printk(KERN_INFO " Call finishup\n"); + printk_debug(" Call finishup\n"); s->super->finishup(s); } } - printk(KERN_INFO "handle_superio done\n"); + printk_debug("handle_superio done\n"); } void @@ -835,12 +864,12 @@ handle_southbridge(int pass, struct southbridge *s, int nsouthbridge) if (!s->southbridge) continue; - printk(KERN_INFO "handle_southbridge: Pass %d, Superio %s\n", pass, + printk_debug("handle_southbridge: Pass %d, Superio %s\n", pass, s->southbridge->name); // need to have both pre_pci_init and devfn defined. if (s->southbridge->pre_pci_init && (pass == 0) && (s->devfn)) { - printk(KERN_INFO " Call pre_pci_init\n"); + printk_debug(" Call pre_pci_init\n"); s->southbridge->pre_pci_init(s); } else @@ -853,7 +882,7 @@ handle_southbridge(int pass, struct southbridge *s, int nsouthbridge) s->southbridge->device, 0); if (! s->device) { // not there! - printk(KERN_INFO " No such device\n"); + printk_info(" No such device\n"); continue; } // problem. We have to handle multiple devices of same type. @@ -863,12 +892,12 @@ handle_southbridge(int pass, struct southbridge *s, int nsouthbridge) // and then continue looking if the device is in use. // For now, let's get this basic thing to work. if (s->southbridge->init && (pass == 1)) { - printk(KERN_INFO " Call init\n"); + printk_debug(" Call init\n"); s->southbridge->init(s); } else if (s->southbridge->finishup && (pass == 2)) { - printk(KERN_INFO " Call finishup\n"); + printk_debug(" Call finishup\n"); s->southbridge->finishup(s); } } diff --git a/src/lib/printk.c b/src/lib/printk.c index 81cc9f4a07..88c0be3403 100644 --- a/src/lib/printk.c +++ b/src/lib/printk.c @@ -12,17 +12,18 @@ static char rcsid[] = "$Id$"; //typedef void * va_list; #include +#include static char buf[1024]; /* printk's without a loglevel use this.. */ -#define DEFAULT_MESSAGE_LOGLEVEL 4 /* KERN_WARNING */ +#define DEFAULT_MESSAGE_LOGLEVEL 4 /* BIOS_WARNING */ /* We show everything that is MORE important than this.. */ #define MINIMUM_CONSOLE_LOGLEVEL 1 /* Minimum loglevel we let people use */ #ifndef DEFAULT_CONSOLE_LOGLEVEL -#define DEFAULT_CONSOLE_LOGLEVEL 8 /* anything MORE serious than KERN_WARNING */ +#define DEFAULT_CONSOLE_LOGLEVEL 8 /* anything MORE serious than BIOS_SPEW */ #endif /* Keep together for sysctl support */ @@ -35,31 +36,27 @@ int default_console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; void display(char*); extern int vsprintf(char *buf, const char *, va_list); -int printk(const char *fmt, ...) +spinlock_t console_lock = SPIN_LOCK_UNLOCKED; + +int do_printk(int msg_level, const char *fmt, ...) { va_list args; int i; - char *p; - int msg_level; + + if (msg_level >= console_loglevel) { + return 0; + } + + spin_lock(&console_lock); va_start(args, fmt); i = vsprintf(buf, fmt, args); /* hopefully i < sizeof(buf)-4 */ va_end(args); - p = buf; - if ( - p[0] == '<' && - p[1] > '0' && - p[1] <= '9' && - p[2] == '>' - ) { - msg_level = p[1] - '0'; - p +=3; - } else { - msg_level = default_message_loglevel; - } - if (msg_level < console_loglevel) { - display(p); - } + + display(buf); + + spin_unlock(&console_lock); + return i; } diff --git a/src/lib/serial_subr.c b/src/lib/serial_subr.c index 97834a5fe5..f417973695 100644 --- a/src/lib/serial_subr.c +++ b/src/lib/serial_subr.c @@ -8,24 +8,6 @@ static char rcsid[] = "$Id$"; /* Base Address */ #define TTYS0 0x3f8 -/* Data */ -#define TTYS0_RBR (TTYS0+0x00) - -/* Control */ -#define TTYS0_TBR TTYS0_RBR -#define TTYS0_IER (TTYS0+0x01) -#define TTYS0_IIR (TTYS0+0x02) -#define TTYS0_FCR TTYS0_IIR -#define TTYS0_LCR (TTYS0+0x03) -#define TTYS0_MCR (TTYS0+0x04) -#define TTYS0_DLL TTYS0_RBR -#define TTYS0_DLM TTYS0_IER - -/* Status */ -#define TTYS0_LSR (TTYS0+0x05) -#define TTYS0_MSR (TTYS0+0x06) -#define TTYS0_SCR (TTYS0+0x07) - #ifndef TTYS0_BAUD #define TTYS0_BAUD 115200 #endif @@ -36,59 +18,177 @@ static char rcsid[] = "$Id$"; #define TTYS0_DIV (115200/TTYS0_BAUD) +/* Data */ +#define UART_RBR 0x00 +#define UART_TBR 0x00 + +/* Control */ +#define UART_IER 0x01 +#define UART_IIR 0x02 +#define UART_FCR 0x02 +#define UART_LCR 0x03 +#define UART_MCR 0x04 +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/* Status */ +#define UART_LSR 0x05 +#define UART_MSR 0x06 +#define UART_SCR 0x07 + +#ifndef TTYS0_BAUD +#define TTYS0_BAUD 115200 +#endif + +static inline int uart_can_tx_byte(unsigned base_port) +{ + return inb(base_port + UART_LSR) & 0x20; +} + +static inline void uart_wait_to_tx_byte(unsigned base_port) +{ + while(!uart_can_tx_byte(base_port)) + ; +} + +static inline void uart_wait_until_sent(unsigned base_port) +{ + while(!(inb(base_port + UART_LSR) & 0x40)) + ; +} + +static inline void uart_tx_byte(unsigned base_port, unsigned char data) +{ + uart_wait_to_tx_byte(base_port); + outb(data, base_port + UART_TBR); + /* Make certain the data clears the fifos */ + uart_wait_until_sent(base_port); +} + +static inline void uart_tx_bytes(unsigned base_port, char *data, unsigned len) +{ + do { + uart_wait_to_tx_byte(base_port); + outb(*data, base_port + UART_TBR); + data++; + len--; + } while(len); + uart_wait_until_sent(base_port); +} + + +static inline int uart_have_rx_byte(unsigned base_port) +{ + return inb(base_port + UART_LSR) & 0x1; +} + +static inline void uart_enable_rx_byte(unsigned base_port) +{ + unsigned char byte; + /* say we are ready for a byte */ + byte = inb(base_port + UART_MCR); + byte |= 0x02; + outb(byte, base_port + UART_MCR); +} + +static inline void uart_disable_rx_byte(unsigned base_port) +{ + unsigned char byte; + /* say we aren't ready for another byte */ + byte = inb(base_port + UART_MCR); + byte &= ~0x02; + outb(byte, base_port + UART_MCR); +} + +static inline void uart_wait_for_rx_byte(unsigned base_port) +{ + uart_enable_rx_byte(base_port); + while(!uart_have_rx_byte(base_port)) + ; + uart_disable_rx_byte(base_port); +} + +static inline unsigned char uart_rx_byte(unsigned base_port) +{ + unsigned char data; + if (!uart_have_rx_byte(base_port)) { + uart_wait_for_rx_byte(base_port); + } + data = inb(base_port + UART_RBR); + return data; +} + +static inline unsigned long uart_rx_bytes(unsigned base_port, + char * buffer, unsigned long size) +{ + unsigned long bytes = 0; + if (size == 0) { + return 0; + } + if (!uart_have_rx_byte(base_port)) { + uart_wait_for_rx_byte(base_port); + } + do { + buffer[bytes++] = inb(base_port + UART_RBR); + } while((bytes < size) && uart_have_rx_byte(base_port)); + return bytes; +} + +inline void uart_init(unsigned base_port, unsigned divisor) +{ + /* disable interrupts */ + outb(0x0, base_port + UART_IER); + /* enable fifo's */ + outb(0x01, base_port + UART_FCR); + /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ + outb(0x83, base_port + UART_LCR); + outb(divisor & 0xFF, base_port + UART_DLL); + outb((divisor >> 8) & 0xFF, base_port + UART_DLM); + outb(0x03, base_port + UART_LCR); +} + +void ttys0_init(void) +{ + uart_init(TTYS0, TTYS0_DIV); +} + +void ttys0_tx_byte(unsigned char data) +{ + uart_tx_byte(TTYS0, data); +} + +unsigned char ttys0_rx_byte(void) +{ + return uart_rx_byte(TTYS0); +} + +unsigned long ttys0_rx_bytes(char *buffer, unsigned long size) +{ + return uart_rx_bytes(TTYS0, buffer, size); +} + #ifdef PYRO_SERIAL - /* experimental serial read stuffs */ -int iskey(void) +int iskey(void) { - if (inb(TTYS0_LSR) & 0x01) - return(1); - - return(0); + return uart_have_rx_byte(TTYS0); } -char ttys0_rx_char(void) +char ttys0_rx_char(void) { - char result; - - while (!(inb(TTYS0_LSR) & 0x01)); - - result = inb(TTYS0_RBR); - return(result); + return ttys0_rx_byte(); } -void ttys0_rx_line(char *buffer, int *len) +void ttys0_rx_line(char *buffer, int *len) { int pos=0; char chargot=0; - while (chargot != '\r' && chargot != '\n' && pos< *len) { + while(chargot != '\r' && chargot != '\n' && pos< *len) { chargot = ttys0_rx_char(); buffer[pos++] = chargot; } *len = pos-1; } - #endif - -void ttys0_init(void) -{ - /* disable interrupts */ - outb(0x0, TTYS0_IER); - /* disable fifo's */ - outb(0x0, TTYS0_FCR); - outb(0x83, TTYS0_LCR); - /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(TTYS0_DIV, TTYS0_DLL); - outb(0, TTYS0_DLM); - outb(0x03, TTYS0_LCR); -} - -void ttys0_tx_byte(unsigned char data) -{ - while (!(inb(TTYS0_LSR) & 0x20)) - ; - outb(data, TTYS0_TBR); -} - diff --git a/src/lib/subr.c b/src/lib/subr.c index eb57e1b824..23bf10aa46 100644 --- a/src/lib/subr.c +++ b/src/lib/subr.c @@ -120,7 +120,7 @@ void post_code(uint8_t value) #ifdef SERIAL_POST unsigned long hi, lo; rdtsc(lo, hi); - printk(KERN_INFO "POST: 0x%02x, TSC Lo: %d, Hi: %d\n", + printk_info("POST: 0x%02x, TSC Lo: %d, Hi: %d\n", value, lo, hi); #endif outb(value, 0x80); diff --git a/src/mainboard/asus/cua/mainboard.c b/src/mainboard/asus/cua/mainboard.c index 5a41cdedaf..46b1a4d66c 100644 --- a/src/mainboard/asus/cua/mainboard.c +++ b/src/mainboard/asus/cua/mainboard.c @@ -6,7 +6,7 @@ void mainboard_fixup() { - printk("intel_mainboard_fixup()\n"); + printk_debug("intel_mainboard_fixup()\n"); #if 0 struct pci_dev *pm_pcidev, *host_bridge_pcidev, *nic_pcidev; // put in the right values for acer stuff diff --git a/src/mainboard/dell/350/mainboard.c b/src/mainboard/dell/350/mainboard.c index 84a0d4ca66..d7c9677e51 100644 --- a/src/mainboard/dell/350/mainboard.c +++ b/src/mainboard/dell/350/mainboard.c @@ -11,7 +11,7 @@ final_mainboard_fixup(void) void final_southbridge_fixup(void); void final_superio_fixup(void); - printk(KERN_INFO "DELL 350\n"); + printk_info("DELL 350\n"); final_southbridge_fixup(); #ifndef USE_NEW_SUPERIO_INTERFACE diff --git a/src/mainboard/intel/l440bx/mainboard.c b/src/mainboard/intel/l440bx/mainboard.c index 3d5d8c98c4..16d9e888c5 100644 --- a/src/mainboard/intel/l440bx/mainboard.c +++ b/src/mainboard/intel/l440bx/mainboard.c @@ -11,7 +11,7 @@ void mainboard_fixup() struct pci_dev *pm_pcidev, *host_bridge_pcidev, *nic_pcidev; unsigned smbus_io, pm_io; unsigned int i, j; - printk("intel_mainboard_fixup()\n"); + printk_debug("intel_mainboard_fixup()\n"); #if 1 pm_pcidev = pci_find_device(0x8086, 0x7113, 0); @@ -28,31 +28,31 @@ void mainboard_fixup() u32 dword; for(i = 0; i < 8; i++) { pci_read_config_byte(host_bridge_pcidev, 0x60 +i, &byte); - printk("DRB[i] = 0x%02x\n", byte); + printk_debug("DRB[i] = 0x%02x\n", byte); } pci_read_config_byte(host_bridge_pcidev, 0x57, &byte); - printk("DRAMC = 0x%02x\n", byte); + printk_debug("DRAMC = 0x%02x\n", byte); pci_read_config_byte(host_bridge_pcidev, 0x74, &byte); - printk("RPS = 0x%02x\n", byte); + printk_debug("RPS = 0x%02x\n", byte); pci_read_config_word(host_bridge_pcidev, 0x78, &word); - printk("PGPOL = 0x%04x\n", word); + printk_debug("PGPOL = 0x%04x\n", word); pci_read_config_dword(host_bridge_pcidev, 0x50, &dword); - printk("NBXCFG = 0x%04x\n", dword); + printk_debug("NBXCFG = 0x%04x\n", dword); } #endif #if 1 - printk("Reset Control Register\n"); + printk_debug("Reset Control Register\n"); outb(((inb(0xcf9) & 0x04) | 0x02), 0xcf9); - printk("port 92\n"); + printk_debug("port 92\n"); outb((inb(0x92) & 0xFE), 0x92); - printk("Disable Nmi\n"); + printk_debug("Disable Nmi\n"); outb(0, 0x70); - printk("enabling smbus\n"); + printk_debug("enabling smbus\n"); #if 0 smbus_io = NewPciIo(0x10); #else @@ -63,7 +63,7 @@ void mainboard_fixup() pci_write_config_word(pm_pcidev, 0x4, 1); /* iospace enable */ - printk("enable pm functions\n"); + printk_debug("enable pm functions\n"); #if 0 pm_io = NewPciIo(0x40); #else @@ -72,13 +72,13 @@ void mainboard_fixup() pci_write_config_dword(pm_pcidev, 0x40, pm_io | 1); /* iobase addr */ pci_write_config_byte(pm_pcidev, 0x80, 1); /* enable pm io address */ - printk("disabling smi\n"); + printk_debug("disabling smi\n"); /* GLBEN */ outw(0x00, pm_io + 0x20); /* GLBCTL */ outl((1 << 24), pm_io + 0x28); - printk("Disable more pm stuff\n"); + printk_debug("Disable more pm stuff\n"); /* PMEN */ outw((1 << 8), pm_io + 0x02); /* PMCNTRL */ @@ -98,10 +98,10 @@ void mainboard_fixup() /* GPIREG */ /* GPOREG */ - printk("Set the subsystem vendor id\n"); + printk_debug("Set the subsystem vendor id\n"); pci_write_config_word(host_bridge_pcidev, 0x2c, 0x8086); - printk("Disabling pm stuff in pci config space\n"); + printk_debug("Disabling pm stuff in pci config space\n"); #define MAX_COUNTERS #ifndef MAX_COUNTERS @@ -162,19 +162,19 @@ void mainboard_fixup() #if 1 /* Verify that smi is disabled */ - printk("Testing SMI\r\n"); + printk_debug("Testing SMI\r\n"); { u32 value; pci_read_config_dword(pm_pcidev, 0x58, &value); pci_write_config_dword(pm_pcidev, 0x58, value | (1 << 25)); } outb(inb(0xb2), 0xb2); - printk("SMI disabled\r\n"); + printk_debug("SMI disabled\r\n"); #endif #if 0 for(i = 0; i < 255; i++) { - printk("%08x\r\n", i); + printk_debug("%08x\r\n", i); __rdtsc_delay2(1000000000UL, pm_io); } #endif diff --git a/src/mainboard/intel/l440gx/Config b/src/mainboard/intel/l440gx/Config index 52ec32e61d..70684c1a3b 100644 --- a/src/mainboard/intel/l440gx/Config +++ b/src/mainboard/intel/l440gx/Config @@ -13,9 +13,12 @@ option NO_KEYBOARD option ZKERNEL_START=0xfff40000 option ZKERNEL_MASK=0x3ed option L440GX -option SMP +option IOAPIC=1 +option SMP=1 +option MAX_CPUS=2 object mainboard.o +object mptable.o cpu p6 cpu p5 diff --git a/src/mainboard/intel/l440gx/mainboard.c b/src/mainboard/intel/l440gx/mainboard.c index 3d5d8c98c4..16d9e888c5 100644 --- a/src/mainboard/intel/l440gx/mainboard.c +++ b/src/mainboard/intel/l440gx/mainboard.c @@ -11,7 +11,7 @@ void mainboard_fixup() struct pci_dev *pm_pcidev, *host_bridge_pcidev, *nic_pcidev; unsigned smbus_io, pm_io; unsigned int i, j; - printk("intel_mainboard_fixup()\n"); + printk_debug("intel_mainboard_fixup()\n"); #if 1 pm_pcidev = pci_find_device(0x8086, 0x7113, 0); @@ -28,31 +28,31 @@ void mainboard_fixup() u32 dword; for(i = 0; i < 8; i++) { pci_read_config_byte(host_bridge_pcidev, 0x60 +i, &byte); - printk("DRB[i] = 0x%02x\n", byte); + printk_debug("DRB[i] = 0x%02x\n", byte); } pci_read_config_byte(host_bridge_pcidev, 0x57, &byte); - printk("DRAMC = 0x%02x\n", byte); + printk_debug("DRAMC = 0x%02x\n", byte); pci_read_config_byte(host_bridge_pcidev, 0x74, &byte); - printk("RPS = 0x%02x\n", byte); + printk_debug("RPS = 0x%02x\n", byte); pci_read_config_word(host_bridge_pcidev, 0x78, &word); - printk("PGPOL = 0x%04x\n", word); + printk_debug("PGPOL = 0x%04x\n", word); pci_read_config_dword(host_bridge_pcidev, 0x50, &dword); - printk("NBXCFG = 0x%04x\n", dword); + printk_debug("NBXCFG = 0x%04x\n", dword); } #endif #if 1 - printk("Reset Control Register\n"); + printk_debug("Reset Control Register\n"); outb(((inb(0xcf9) & 0x04) | 0x02), 0xcf9); - printk("port 92\n"); + printk_debug("port 92\n"); outb((inb(0x92) & 0xFE), 0x92); - printk("Disable Nmi\n"); + printk_debug("Disable Nmi\n"); outb(0, 0x70); - printk("enabling smbus\n"); + printk_debug("enabling smbus\n"); #if 0 smbus_io = NewPciIo(0x10); #else @@ -63,7 +63,7 @@ void mainboard_fixup() pci_write_config_word(pm_pcidev, 0x4, 1); /* iospace enable */ - printk("enable pm functions\n"); + printk_debug("enable pm functions\n"); #if 0 pm_io = NewPciIo(0x40); #else @@ -72,13 +72,13 @@ void mainboard_fixup() pci_write_config_dword(pm_pcidev, 0x40, pm_io | 1); /* iobase addr */ pci_write_config_byte(pm_pcidev, 0x80, 1); /* enable pm io address */ - printk("disabling smi\n"); + printk_debug("disabling smi\n"); /* GLBEN */ outw(0x00, pm_io + 0x20); /* GLBCTL */ outl((1 << 24), pm_io + 0x28); - printk("Disable more pm stuff\n"); + printk_debug("Disable more pm stuff\n"); /* PMEN */ outw((1 << 8), pm_io + 0x02); /* PMCNTRL */ @@ -98,10 +98,10 @@ void mainboard_fixup() /* GPIREG */ /* GPOREG */ - printk("Set the subsystem vendor id\n"); + printk_debug("Set the subsystem vendor id\n"); pci_write_config_word(host_bridge_pcidev, 0x2c, 0x8086); - printk("Disabling pm stuff in pci config space\n"); + printk_debug("Disabling pm stuff in pci config space\n"); #define MAX_COUNTERS #ifndef MAX_COUNTERS @@ -162,19 +162,19 @@ void mainboard_fixup() #if 1 /* Verify that smi is disabled */ - printk("Testing SMI\r\n"); + printk_debug("Testing SMI\r\n"); { u32 value; pci_read_config_dword(pm_pcidev, 0x58, &value); pci_write_config_dword(pm_pcidev, 0x58, value | (1 << 25)); } outb(inb(0xb2), 0xb2); - printk("SMI disabled\r\n"); + printk_debug("SMI disabled\r\n"); #endif #if 0 for(i = 0; i < 255; i++) { - printk("%08x\r\n", i); + printk_debug("%08x\r\n", i); __rdtsc_delay2(1000000000UL, pm_io); } #endif diff --git a/src/mainboard/intel/l440gx/mptable.c b/src/mainboard/intel/l440gx/mptable.c index c80157671b..1b2cab481c 100644 --- a/src/mainboard/intel/l440gx/mptable.c +++ b/src/mainboard/intel/l440gx/mptable.c @@ -3,7 +3,7 @@ void smp_write_config_table(void *v) { - int ioapicid = 0; // JAMES_HACK + int ioapicid = 0; static const char sig[4] = "PCMP"; static const char oem[8] = "LNXI "; static const char productid[12] = "L440GX "; @@ -26,18 +26,9 @@ void smp_write_config_table(void *v) mc->mpe_checksum = 0; mc->reserved = 0; -#ifndef JAMES_HACK - smp_write_processor(mc, 0x01, 0x11, - CPU_ENABLED | CPU_BOOTPROCESSOR, 0x00000683, 0x0387fbff); -#else - printk("James: Setting up 2 proc. SMP table"); - smp_write_processor(mc, 0x1, 0x11, - CPU_ENABLED | CPU_BOOTPROCESSOR, 0x00000683, 0x0387fbff); - smp_write_processor(mc, 0x0, 0x11, - CPU_ENABLED, 0x00000683, 0x0387fbff); + smp_write_processors(mc); ioapicid = 2; -#endif smp_write_bus(mc, 0, "PCI "); smp_write_bus(mc, 1, "PCI "); @@ -126,6 +117,8 @@ void smp_write_config_table(void *v) mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); } void write_smp_table(void *v) diff --git a/src/mainboard/irobot/proto1/mainboard.c b/src/mainboard/irobot/proto1/mainboard.c index 905907ddfe..b6d9c33034 100644 --- a/src/mainboard/irobot/proto1/mainboard.c +++ b/src/mainboard/irobot/proto1/mainboard.c @@ -100,7 +100,7 @@ loader_setup(unsigned long base, button = !(inb(0x4031) & 0x04); - PRINTK(KERN_INFO "LID button is - %s\n", (button ? "closed" : "open")); + printk_info( "LID button is - %s\n", (button ? "closed" : "open")); if (button) { *cmd_line = "root=/dev/ram0 console=ttyS0,115200"; @@ -114,7 +114,7 @@ loader_setup(unsigned long base, /* flip to other flash page */ gpo0 = inb(0x4034); - PRINTK(KERN_INFO "GPO[0] : 0x%02x\n", gpo0); + printk_info( "GPO[0] : 0x%02x\n", gpo0); gpo0 &= ~0x01; outb(gpo0, 0x4034); @@ -122,10 +122,10 @@ loader_setup(unsigned long base, int ii; for (ii = 0; ii<16; ii++) { - PRINTK(KERN_INFO "[%02x] ", *(unsigned char *)(0xfff00000+ii)); + printk_info( "[%02x] ", *(unsigned char *)(0xfff00000+ii)); } - PRINTK(KERN_INFO "\n"); + printk_info("\n"); } memcpy((void *)(*initrd_start), (void *)(0xfff00000), *initrd_size); diff --git a/src/mainboard/leadtek/winfast6300/mainboard.c b/src/mainboard/leadtek/winfast6300/mainboard.c index 67d59c6723..6cb51e1f93 100644 --- a/src/mainboard/leadtek/winfast6300/mainboard.c +++ b/src/mainboard/leadtek/winfast6300/mainboard.c @@ -11,8 +11,7 @@ final_mainboard_fixup(void) void final_southbridge_fixup(void); void final_superio_fixup(void); - printk(KERN_INFO - "Winfast 6300 (and similar)..."); + printk_info("Winfast 6300 (and similar)..."); final_southbridge_fixup(); #ifndef USE_NEW_SUPERIO_INTERFACE diff --git a/src/mainboard/matsonic/ms7308e/mainboard.c b/src/mainboard/matsonic/ms7308e/mainboard.c index a76b0e8adf..87ef89fc5c 100644 --- a/src/mainboard/matsonic/ms7308e/mainboard.c +++ b/src/mainboard/matsonic/ms7308e/mainboard.c @@ -11,8 +11,7 @@ final_mainboard_fixup(void) void final_southbridge_fixup(void); void final_superio_fixup(void); - printk(KERN_INFO - "Matsonic MS7308E (and similar)"); + printk_info("Matsonic MS7308E (and similar)"); final_southbridge_fixup(); #ifndef USE_NEW_SUPERIO_INTERFACE diff --git a/src/mainboard/pcchips/m754lmr/mainboard.c b/src/mainboard/pcchips/m754lmr/mainboard.c index 32f7fb2f4c..0ab7fd072d 100644 --- a/src/mainboard/pcchips/m754lmr/mainboard.c +++ b/src/mainboard/pcchips/m754lmr/mainboard.c @@ -6,7 +6,7 @@ void mainboard_fixup() { - printk("mainboard_fixup()\n"); + printk_info("mainboard_fixup()\n"); } void final_mainboard_fixup() diff --git a/src/mainboard/pcchips/m810lmr/mainboard.c b/src/mainboard/pcchips/m810lmr/mainboard.c index 9b70831186..c080d00a5a 100644 --- a/src/mainboard/pcchips/m810lmr/mainboard.c +++ b/src/mainboard/pcchips/m810lmr/mainboard.c @@ -11,7 +11,7 @@ final_mainboard_fixup(void) void final_southbridge_fixup(void); void final_superio_fixup(void); - printk(KERN_INFO "PCCHIPS M810LMR (and similar)..."); + printk_info("PCCHIPS M810LMR (and similar)..."); final_southbridge_fixup(); #ifndef USE_NEW_SUPERIO_INTERFACE diff --git a/src/mainboard/sis/540/mainboard.c b/src/mainboard/sis/540/mainboard.c index 32805afb41..c5d34f309e 100644 --- a/src/mainboard/sis/540/mainboard.c +++ b/src/mainboard/sis/540/mainboard.c @@ -11,8 +11,7 @@ final_mainboard_fixup(void) void final_southbridge_fixup(void); void final_superio_fixup(void); - printk(KERN_INFO - "SiS 540 (and similar)..."); + printk_info("SiS 540 (and similar)..."); final_southbridge_fixup(); #ifndef USE_NEW_SUPERIO_INTERFACE diff --git a/src/mainboard/sis/550/mainboard.c b/src/mainboard/sis/550/mainboard.c index dc0f997f1e..c5148a8702 100644 --- a/src/mainboard/sis/550/mainboard.c +++ b/src/mainboard/sis/550/mainboard.c @@ -10,8 +10,7 @@ final_mainboard_fixup(void) { void final_southbridge_fixup(void); - printk(KERN_INFO - "SiS 550 (and similar)..."); + printk_info("SiS 550 (and similar)..."); final_southbridge_fixup(); } diff --git a/src/northbridge/acer/m1631/northbridge.c b/src/northbridge/acer/m1631/northbridge.c index f8714cac25..b9acb8096f 100644 --- a/src/northbridge/acer/m1631/northbridge.c +++ b/src/northbridge/acer/m1631/northbridge.c @@ -13,7 +13,7 @@ void refresh_set(int turn_it_on) return; pci_read_config_dword(pcidev, 0x7c, &ref); -// printk(KERN_INFO __FUNCTION__ "refresh was 0x%lx onoff is %d\n", +// printk_info( __FUNCTION__ "refresh was 0x%lx onoff is %d\n", // ref, turn_it_on); if (turn_it_on) ref |= (1 << 19); @@ -22,7 +22,7 @@ void refresh_set(int turn_it_on) pci_write_config_dword(pcidev, 0x7c, ref); pci_read_config_dword(pcidev, 0x7c, &ref); -// printk(KERN_INFO __FUNCTION__ "refresh is now 0x%lx\n", ref); +// printk_info( __FUNCTION__ "refresh is now 0x%lx\n", ref); } // FIX ME! unsigned long sizeram() @@ -39,7 +39,7 @@ unsigned long sizeram() if (! pcidev) return 0; - printk("Acer sizeram pcidev %p\n", pcidev); + printk_info("Acer sizeram pcidev %p\n", pcidev); /* now read and print registers for ram ...*/ for(i = 0x6c; i < 0x78; i += 4) { @@ -48,7 +48,7 @@ unsigned long sizeram() size = (1 << (((ram >> 20) & 0x7))) * (0x400000); if ((ram & 0x6000000) == 0x00000000) size=0; - printk("0x%x 0x%x, size 0x%x\n", i, ram, size); + printk_info("0x%x 0x%x, size 0x%x\n", i, ram, size); } for(i = 0x6c; i < 0x78; i +=4) @@ -60,7 +60,7 @@ unsigned long sizeram() if ((ram & 0x6000000) == 0x00000000) size=0; - printk("size in 0x%x is 0x%x\n", i, size); + printk_info("size in 0x%x is 0x%x\n", i, size); sizeall=sizeall+size; } return sizeall/1024; @@ -71,13 +71,13 @@ unsigned long sizeram() u32 temp; u8 c1, c2; unsigned long size, cas, offset; - printk("OK, let's try the other two banks\n"); + printk_debug("OK, let's try the other two banks\n"); pci_read_config_dword(pcidev, i, &temp); pci_write_config_dword(pcidev, i, INIT_MCR); - printk("Slot 0x%x: set to 0x%x\n", i, INIT_MCR); + printk_debug("Slot 0x%x: set to 0x%x\n", i, INIT_MCR); // anyone home? cache_disable(); - printk("Slot 0x%x: set value at %p\n", i, cp); + printk_debug("Slot 0x%x: set value at %p\n", i, cp); refresh_set(0); *cp = 0x55; *(cp + 8) = 0xaa; @@ -85,26 +85,26 @@ unsigned long sizeram() c2 = *(cp + 8); refresh_set(1); cache_enable(); - printk("Slot 0x%x: value at %p is 0x%x\n", i, cp, c1); - printk("Slot 0x%x: value at %p is 0x%x\n", i, cp+8, c2); + printk_debug("Slot 0x%x: value at %p is 0x%x\n", i, cp, c1); + printk_debug("Slot 0x%x: value at %p is 0x%x\n", i, cp+8, c2); if ((c1 != 0x55) || (c2 != 0xaa)) { - printk("Nothing in slot 0x%x\n", i); + printk_debug("Nothing in slot 0x%x\n", i); pci_write_config_dword(pcidev, i, temp); continue; } // get the cas bank size. for(cas = 0, offset = 0x800; ;cas++, offset <<= 1) { *cp = 0; - printk("Slot %x: check at %p\n", i, (cp+offset)); + printk_debug("Slot %x: check at %p\n", i, (cp+offset)); *(cp + offset) = cas + 1; - printk("Slot %x: cas %d, *cp %d\n", i, cas, *cp); + printk_debug("Slot %x: cas %d, *cp %d\n", i, cas, *cp); if (*cp) break; if (cas > 2) break; } - printk("Slot 0x%x: cas is 0x%x\n", i, cas); + printk_debug("Slot 0x%x: cas is 0x%x\n", i, cas); // now set the cas value into bits 19:16 cas <<= 16; pci_read_config_dword(pcidev, i, &temp); @@ -118,43 +118,43 @@ unsigned long sizeram() if (*cp) break; } - printk("Slot 0x%x: size 0x%x\n", i, size); + printk_debug("Slot 0x%x: size 0x%x\n", i, size); // fix up size bits temp &= ~0x700000; temp |= size << 20; temp |= 1; temp &= ~0x1000; pci_write_config_dword(pcidev, i, temp); - printk("Slot 0x%x: before banks wrote 0x%x\n", i, temp); + printk_debug("Slot 0x%x: before banks wrote 0x%x\n", i, temp); // now see what the banks are. *cp = 0; *(cp + 0x1000) = 5; *(cp + 0x2000) = 6; *(cp + 0x4000) = 7; if (*cp) { - printk("Slot 0x%x: two banks\n", i); + printk_debug("Slot 0x%x: two banks\n", i); // only two banks temp &= ~1; pci_write_config_dword(pcidev, i, temp); } else - printk("Slot 0x%x: four banks\n", i); + printk_debug("Slot 0x%x: four banks\n", i); // compute real size size = (1< 62.4 us */ .byte 0x04 /* Extended(8x) 125 us -> 124.8 us */ +#if USE_SPD spd_enable_refresh: /* Find the first dimm and assume the rest are the same */ /* Load the smbus device and port int %ebx */ @@ -940,6 +950,10 @@ spd_set_nbxcfg: spd_set_sdramc: RET_LABEL(spd_set_sdramc) +#endif /* USE_SPD */ + + + /* PAM FDHC MBSC SMRAM ESRAMC MBFS DWTC DRTC */ ram_set_spd_registers: #if USE_SPD @@ -954,6 +968,18 @@ ram_set_spd_registers: #endif RET_LABEL(ram_set_spd_registers) +#if 1 +#define HAVE_ECC_RAM_SIZE +get_ecc_ram_size_ebx: + movl $0x67, %eax /* Read the RAM SIZE */ + PCI_READ_CONFIG_BYTE + andl $0x000000ff, %eax /* Convert it to bytes */ + movl %eax, %ebx + shll $23, %ebx + RET_LABEL(get_ecc_ram_size_ebx) +#endif /* HAVE_ECC_RAM_SIZE */ + + /* things that are not used */ #define FIRST_NORMAL_REFERENCE() #define SPECIAL_FINISHUP() diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 86a7e2beda..692de36ee8 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -31,9 +31,9 @@ unsigned long sizeram() // sanity check. If the mem value is < prevmem, // that is an error, so skip this step. if (mem < prevmem) { - printk("ERROR: bank 0x%x, mem 0x%x TOO SMALL\n", + printk_err("ERROR: bank 0x%x, mem 0x%x TOO SMALL\n", bank, prevmem); - printk("Should be >= 0x%x\n", prevmem); + printk_err("Should be >= 0x%x\n", prevmem); } else totalmem += (mem - prevmem) * 8; prevmem = mem; @@ -42,11 +42,11 @@ unsigned long sizeram() totalmem -= sma_size; totalmem *= 1024; - printk("sizeram: returning 0x%x KB\n", totalmem); - printk("sizeram: NOT returning 0x%x KB\n", totalmem); - printk("sizeram: there are still some SPD problems ... \n"); + printk_info("sizeram: returning 0x%x KB\n", totalmem); + printk_info("sizeram: NOT returning 0x%x KB\n", totalmem); + printk_info("sizeram: there are still some SPD problems ... \n"); totalmem = 64 * 1024; - printk("sizeram: SO we return only 0x%x KB\n", totalmem); + printk_info("sizeram: SO we return only 0x%x KB\n", totalmem); #if 0 #endif return totalmem; diff --git a/src/northsouthbridge/sis/540/southbridge.c b/src/northsouthbridge/sis/540/southbridge.c index 5999b8d44e..87151b622d 100644 --- a/src/northsouthbridge/sis/540/southbridge.c +++ b/src/northsouthbridge/sis/540/southbridge.c @@ -48,16 +48,16 @@ void nvram_on() pci_write_config_byte(pcidev, 0x40, 0x33); /* Flash can be flashed */ pci_write_config_byte(pcidev, 0x45, 0x40); - DBG("Enabled in SIS 503 regs 0x40 and 0x45\n"); + printk_debug("Enabled in SIS 503 regs 0x40 and 0x45\n"); } - DBG("Now try to turn off shadow\n"); + printk_debug("Now try to turn off shadow\n"); #ifdef USE_DOC_MIL /* turn off nvram shadow in 0xc0000 ~ 0xfffff, i.e. accessing segment C - F is actually to the DRAM not NVRAM. For 512KB NVRAM case, this one should be disabled */ pcidev = pci_find_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_540, (void *)NULL); - DBG("device for SiS 540 is 0x%x\n", pcidev); + printk_debug("device for SiS 540 is 0x%x\n", pcidev); if (pcidev != NULL) { /* read cycle goes to System Memory */ /* write cycle goest to System Memory */ @@ -65,7 +65,7 @@ void nvram_on() pci_write_config_word(pcidev, 0x72, 0xFFFF); pci_write_config_word(pcidev, 0x74, 0xFFFF); pci_write_config_byte(pcidev, 0x76, 0xFF); - DBG("Shadow memory disabled in SiS 540\n"); + printk_debug("Shadow memory disabled in SiS 540\n"); } #endif @@ -110,21 +110,21 @@ acpi_fixup(void) // Set a base address for ACPI of 0xc000 pci_read_config_word(pcidev, 0x74, &temp); - DBG("acpibase was 0x%x\n", temp); + printk_debug("acpibase was 0x%x\n", temp); pci_write_config_word(pcidev, 0x74, acpibase); pci_read_config_word(pcidev, 0x74, &temp); - DBG("acpibase is 0x%x\n", temp); + printk_debug("acpibase is 0x%x\n", temp); // now enable acpi pci_read_config_byte(pcidev, 0x40, &val); - DBG("acpi enable reg was 0x%x\n", val); + printk_debug("acpi enable reg was 0x%x\n", val); val |= 0x80; pci_write_config_byte(pcidev, 0x40, val); pci_read_config_byte(pcidev, 0x40, &val); - DBG("acpi enable reg after set is 0x%x\n", val); - DBG("acpi status: word at 0x56 is 0x%x\n", + printk_debug("acpi enable reg after set is 0x%x\n", val); + printk_debug("acpi status: word at 0x56 is 0x%x\n", inw(acpibase+0x56)); - DBG("acpi status: byte at 0x4b is 0x%x\n", + printk_debug("acpi status: byte at 0x4b is 0x%x\n", inb(acpibase + 0x4b)); // now that it's on, get in there and call off the dogs. @@ -134,14 +134,14 @@ acpi_fixup(void) outb(0, acpibase + 0x4b); // ah ha! have to SET, NOT CLEAR! outb(0x40, acpibase + 0x56); - DBG("acpibase + 0x56 is 0x%x\n", + printk_debug("acpibase + 0x56 is 0x%x\n", inb(acpibase+0x56)); val &= (~0x80); pci_write_config_byte(pcidev, 0x40, val); pci_read_config_byte(pcidev, 0x40, &val); - DBG("acpi disable reg after set is 0x%x\n", val); + printk_debug("acpi disable reg after set is 0x%x\n", val); } else { - printk(KERN_EMERG "Can't find south bridge!\n"); + printk_emerg("Can't find south bridge!\n"); } } @@ -155,5 +155,5 @@ final_southbridge_fixup() serial_irq_fixedup(); acpi_fixup(); - DBG("Southbridge fixup done for SIS 503\n"); + printk_debug("Southbridge fixup done for SIS 503\n"); } diff --git a/src/northsouthbridge/sis/550/southbridge.c b/src/northsouthbridge/sis/550/southbridge.c index 4e0507125a..dee421dcc0 100644 --- a/src/northsouthbridge/sis/550/southbridge.c +++ b/src/northsouthbridge/sis/550/southbridge.c @@ -48,17 +48,17 @@ void nvram_on() pci_write_config_byte(pcidev, 0x40, 0x33); /* Flash can be flashed */ pci_write_config_byte(pcidev, 0x45, 0x40); - DBG("Enabled in SIS 503 regs 0x40 and 0x45\n"); + printk_debug("Enabled in SIS 503 regs 0x40 and 0x45\n"); } - DBG("Now try to turn off shadow\n"); + printk_debug("Now try to turn off shadow\n"); #ifdef USE_DOC_MIL /* turn off nvram shadow in 0xc0000 ~ 0xfffff, i.e. accessing segment C - F is actually to the DRAM not NVRAM. For 512KB NVRAM case, this one should be disabled */ pcidev = pci_find_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_550, (void *)NULL); - DBG("device for SiS 550 is 0x%x\n", pcidev); + printk_debug("device for SiS 550 is 0x%x\n", pcidev); if (pcidev != NULL) { /* read cycle goes to System Memory */ //pci_write_config_word(pcidev, 0x70, 0x1fff); @@ -68,7 +68,7 @@ void nvram_on() pci_write_config_word(pcidev, 0x72, 0xFFFF); pci_write_config_word(pcidev, 0x74, 0xFFFF); pci_write_config_byte(pcidev, 0x76, 0xFF); - DBG("Shadow memory disabled in SiS 550\n"); + printk_debug("Shadow memory disabled in SiS 550\n"); } #endif @@ -132,21 +132,21 @@ acpi_fixup(void) // Set a base address for ACPI of 0xc000 pci_read_config_word(pcidev, 0x74, &temp); - DBG("acpibase was 0x%x\n", temp); + printk_debug("acpibase was 0x%x\n", temp); pci_write_config_word(pcidev, 0x74, acpibase); pci_read_config_word(pcidev, 0x74, &temp); - DBG("acpibase is 0x%x\n", temp); + printk_debug("acpibase is 0x%x\n", temp); // now enable acpi pci_read_config_byte(pcidev, 0x40, &val); - DBG("acpi enable reg was 0x%x\n", val); + printk_debug("acpi enable reg was 0x%x\n", val); val |= 0x80; pci_write_config_byte(pcidev, 0x40, val); pci_read_config_byte(pcidev, 0x40, &val); - DBG("acpi enable reg after set is 0x%x\n", val); - DBG("acpi status: word at 0x56 is 0x%x\n", + printk_debug("acpi enable reg after set is 0x%x\n", val); + printk_debug("acpi status: word at 0x56 is 0x%x\n", inw(acpibase+0x56)); - DBG("acpi status: byte at 0x4b is 0x%x\n", + printk_debug("acpi status: byte at 0x4b is 0x%x\n", inb(acpibase + 0x4b)); // now that it's on, get in there and call off the dogs. @@ -156,14 +156,14 @@ acpi_fixup(void) outb(0, acpibase + 0x4b); // ah ha! have to SET, NOT CLEAR! outb(0x40, acpibase + 0x56); - DBG("acpibase + 0x56 is 0x%x\n", + printk_debug("acpibase + 0x56 is 0x%x\n", inb(acpibase+0x56)); val &= (~0x80); pci_write_config_byte(pcidev, 0x40, val); pci_read_config_byte(pcidev, 0x40, &val); - DBG("acpi disable reg after set is 0x%x\n", val); + printk_debug("acpi disable reg after set is 0x%x\n", val); } else { - printk(KERN_EMERG "Can't find south bridge!\n"); + printk_emerg("Can't find south bridge!\n"); } } @@ -180,5 +180,5 @@ final_southbridge_fixup() /* Delay transaction, experimental */ south_fixup(); - DBG("Southbridge fixup done for SIS 503\n"); + printk_debug("Southbridge fixup done for SIS 503\n"); } diff --git a/src/northsouthbridge/sis/630/southbridge.c b/src/northsouthbridge/sis/630/southbridge.c index ef4ea506c6..64ecba15d3 100644 --- a/src/northsouthbridge/sis/630/southbridge.c +++ b/src/northsouthbridge/sis/630/southbridge.c @@ -48,23 +48,23 @@ void nvram_on() pci_write_config_byte(pcidev, 0x40, 0x33); /* Flash can be flashed */ pci_write_config_byte(pcidev, 0x45, 0x40); - DBG("Enabled in SIS 503 regs 0x40 and 0x45\n"); + printk_debug("Enabled in SIS 503 regs 0x40 and 0x45\n"); } - DBG("Now try to turn off shadow\n"); + printk_debug("Now try to turn off shadow\n"); #ifdef USE_DOC_MIL /* turn off nvram shadow in 0xc0000 ~ 0xfffff, i.e. accessing segment C - F is actually to the DRAM not NVRAM. For 512KB NVRAM case, this one should be disabled */ pcidev = pci_find_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_630, (void *)NULL); - DBG("device for SiS 630 is 0x%x\n", pcidev); + printk_debug("device for SiS 630 is 0x%x\n", pcidev); if (pcidev != NULL) { /* read cycle goes to System Memory */ pci_write_config_word(pcidev, 0x70, 0x1fff); /* write cycle goest to System Memory */ pci_write_config_word(pcidev, 0x72, 0x1fff); - DBG("Shadow memory disabled in SiS 630\n"); + printk_debug("Shadow memory disabled in SiS 630\n"); } #endif @@ -216,21 +216,21 @@ acpi_fixup(void) // Set a base address for ACPI of 0xc000 pci_read_config_word(pcidev, 0x74, &temp); - DBG("acpibase was 0x%x\n", temp); + printk_debug("acpibase was 0x%x\n", temp); pci_write_config_word(pcidev, 0x74, acpibase); pci_read_config_word(pcidev, 0x74, &temp); - DBG("acpibase is 0x%x\n", temp); + printk_debug("acpibase is 0x%x\n", temp); // now enable acpi pci_read_config_byte(pcidev, 0x40, &val); - DBG("acpi enable reg was 0x%x\n", val); + printk_debug("acpi enable reg was 0x%x\n", val); val |= 0x80; pci_write_config_byte(pcidev, 0x40, val); pci_read_config_byte(pcidev, 0x40, &val); - DBG("acpi enable reg after set is 0x%x\n", val); - DBG("acpi status: word at 0x56 is 0x%x\n", + printk_debug("acpi enable reg after set is 0x%x\n", val); + printk_debug("acpi status: word at 0x56 is 0x%x\n", inw(acpibase+0x56)); - DBG("acpi status: byte at 0x4b is 0x%x\n", + printk_debug("acpi status: byte at 0x4b is 0x%x\n", inb(acpibase + 0x4b)); // now that it's on, get in there and call off the dogs. @@ -240,14 +240,14 @@ acpi_fixup(void) outb(0, acpibase + 0x4b); // ah ha! have to SET, NOT CLEAR! outb(0x40, acpibase + 0x56); - DBG("acpibase + 0x56 is 0x%x\n", + printk_debug("acpibase + 0x56 is 0x%x\n", inb(acpibase+0x56)); val &= (~0x80); pci_write_config_byte(pcidev, 0x40, val); pci_read_config_byte(pcidev, 0x40, &val); - DBG("acpi disable reg after set is 0x%x\n", val); + printk_debug("acpi disable reg after set is 0x%x\n", val); } else { - printk(KERN_EMERG "Can't find south bridge!\n"); + printk_emerg("Can't find south bridge!\n"); } } @@ -261,7 +261,7 @@ final_southbridge_fixup() pcidev = pci_find_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, (void *)NULL); if (pcidev != NULL) { - printk("Remapping IRQ on southbridge for OLD_KERNEL_HACK\n"); + printk_info("Remapping IRQ on southbridge for OLD_KERNEL_HACK\n"); // remap IRQ for PCI -- this is exactly what the BIOS does now. pci_write_config_byte(pcidev, 0x42, 0xa); pci_write_config_byte(pcidev, 0x43, 0xb); @@ -285,7 +285,7 @@ final_southbridge_fixup() // set the interrupt to 'b' pci_write_config_byte(pcidev, PCI_INTERRUPT_LINE, 0xb); } else { - printk(KERN_ERR "Can't find ethernet interface\n"); + printk_err("Can't find ethernet interface\n"); } #endif /* OLD_KERNEL_HACK */ @@ -295,5 +295,5 @@ final_southbridge_fixup() serial_irq_fixedup(); acpi_fixup(); - DBG("Southbridge fixup done for SIS 503\n"); + printk_debug("Southbridge fixup done for SIS 503\n"); } diff --git a/src/northsouthbridge/sis/730/southbridge.c b/src/northsouthbridge/sis/730/southbridge.c index bcd1d18ee4..5f10bc6041 100644 --- a/src/northsouthbridge/sis/730/southbridge.c +++ b/src/northsouthbridge/sis/730/southbridge.c @@ -48,23 +48,23 @@ void nvram_on() pci_write_config_byte(pcidev, 0x40, 0x33); /* Flash can be flashed */ pci_write_config_byte(pcidev, 0x45, 0x40); - DBG("Enabled in SIS 503 regs 0x40 and 0x45\n"); + printk_debug("Enabled in SIS 503 regs 0x40 and 0x45\n"); } - DBG("Now try to turn off shadow\n"); + printk_debug("Now try to turn off shadow\n"); #ifdef USE_DOC_MIL /* turn off nvram shadow in 0xc0000 ~ 0xfffff, i.e. accessing segment C - F is actually to the DRAM not NVRAM. For 512KB NVRAM case, this one should be disabled */ pcidev = pci_find_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_730, (void *)NULL); - DBG("device for SiS 730 is 0x%x\n", pcidev); + printk_debug("device for SiS 730 is 0x%x\n", pcidev); if (pcidev != NULL) { /* read cycle goes to System Memory */ pci_write_config_word(pcidev, 0x70, 0x1fff); /* write cycle goest to System Memory */ pci_write_config_word(pcidev, 0x72, 0x1fff); - DBG("Shadow memory disabled in SiS 730\n"); + printk_debug("Shadow memory disabled in SiS 730\n"); } #endif @@ -205,21 +205,21 @@ acpi_fixup(void) // Set a base address for ACPI of 0xc000 pci_read_config_word(pcidev, 0x74, &temp); - DBG("acpibase was 0x%x\n", temp); + printk_debug("acpibase was 0x%x\n", temp); pci_write_config_word(pcidev, 0x74, acpibase); pci_read_config_word(pcidev, 0x74, &temp); - DBG("acpibase is 0x%x\n", temp); + printk_debug("acpibase is 0x%x\n", temp); // now enable acpi pci_read_config_byte(pcidev, 0x40, &val); - DBG("acpi enable reg was 0x%x\n", val); + printk_debug("acpi enable reg was 0x%x\n", val); val |= 0x80; pci_write_config_byte(pcidev, 0x40, val); pci_read_config_byte(pcidev, 0x40, &val); - DBG("acpi enable reg after set is 0x%x\n", val); - DBG("acpi status: word at 0x56 is 0x%x\n", + printk_debug("acpi enable reg after set is 0x%x\n", val); + printk_debug("acpi status: word at 0x56 is 0x%x\n", inw(acpibase+0x56)); - DBG("acpi status: byte at 0x4b is 0x%x\n", + printk_debug("acpi status: byte at 0x4b is 0x%x\n", inb(acpibase + 0x4b)); // now that it's on, get in there and call off the dogs. @@ -229,14 +229,14 @@ acpi_fixup(void) outb(0, acpibase + 0x4b); // ah ha! have to SET, NOT CLEAR! outb(0x40, acpibase + 0x56); - DBG("acpibase + 0x56 is 0x%x\n", + printk_debug("acpibase + 0x56 is 0x%x\n", inb(acpibase+0x56)); val &= (~0x80); pci_write_config_byte(pcidev, 0x40, val); pci_read_config_byte(pcidev, 0x40, &val); - DBG("acpi disable reg after set is 0x%x\n", val); + printk_debug("acpi disable reg after set is 0x%x\n", val); } else { - printk(KERN_EMERG "Can't find south bridge!\n"); + printk_emerg("Can't find south bridge!\n"); } } @@ -250,7 +250,7 @@ final_southbridge_fixup() pcidev = pci_find_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, (void *)NULL); if (pcidev != NULL) { - printk("Remapping IRQ on southbridge for OLD_KERNEL_HACK\n"); + printk_info("Remapping IRQ on southbridge for OLD_KERNEL_HACK\n"); // remap IRQ for PCI -- this is exactly what the BIOS does now. pci_write_config_byte(pcidev, 0x42, 0xa); pci_write_config_byte(pcidev, 0x43, 0xb); @@ -274,7 +274,7 @@ final_southbridge_fixup() // set the interrupt to 'b' pci_write_config_byte(pcidev, PCI_INTERRUPT_LINE, 0xb); } else { - printk(KERN_ERR "Can't find ethernet interface\n"); + printk_err("Can't find ethernet interface\n"); } #endif /* OLD_KERNEL_HACK */ @@ -284,5 +284,5 @@ final_southbridge_fixup() serial_irq_fixedup(); acpi_fixup(); - DBG("Southbridge fixup done for SIS 503\n"); + printk_debug("Southbridge fixup done for SIS 503\n"); } diff --git a/src/pc80/serial.inc b/src/pc80/serial.inc index 805e7782d0..12057a06fb 100644 --- a/src/pc80/serial.inc +++ b/src/pc80/serial.inc @@ -33,13 +33,25 @@ mov %ah, %al ; \ outb %al, %dx + + /* uses: esp, ax, dx */ +#define TTYS0_TX_CHAR(byte) \ + mov byte, %al ; \ + CALLSP(ttys0_tx_al) + /* uses: ax, dx */ -#define TTYS0_TX_BYTE(byte) \ +#define TTYS0_INLINE_TX_CHAR(byte) \ mov byte, %al ; \ TTYS0_TX_AL + /* uses: esp, ax, dx */ +#define TTYS0_TX_HEX8(byte) \ + mov byte, %al ; \ + CALLSP(ttys0_tx_hex8) + /* uses: ax, dx */ -#define TTYS0_TX_AL_HEX8 \ +#define TTYS0_INLINE_TX_HEX8(byte) \ + mov byte, %al ; \ mov $TTYS0_SCR, %dx ; \ outb %al, %dx ; \ shr $4, %al ; \ @@ -61,27 +73,109 @@ mov $TTYS0_SCR, %dx ; \ inb %dx, %al - - /* uses: esp, ax, dx */ -#define TTYS0_TX_CHAR(byte) \ - mov byte, %al ; \ - CALLSP(ttys0_tx_al) - - /* uses: esp, ax, dx */ -#define TTYS0_TX_HEX8(byte) \ - mov byte, %al ; \ - CALLSP(ttys0_tx_hex8) - /* uses: esp, eax, ebx, dx */ #define TTYS0_TX_HEX32(lword) \ mov lword, %eax ; \ CALLSP(ttys0_tx_hex32) + /* uses: eax, lword, dx */ +#define TTYS0_INLINE_TX_HEX32(lword) \ + mov lword, %eax ; \ + shr $28, %eax ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + TTYS0_TX_AL ; \ + ; \ + mov lword, %eax ; \ + shr $24, %eax ; \ + and $0x0f, %al ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + TTYS0_TX_AL ; \ + ; \ + mov lword, %eax ; \ + shr $20, %eax ; \ + and $0x0f, %al ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + TTYS0_TX_AL ; \ + ; \ + mov lword, %eax ; \ + shr $16, %eax ; \ + and $0x0f, %al ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + TTYS0_TX_AL ; \ + ; \ + mov lword, %eax ; \ + shr $12, %eax ; \ + and $0x0f, %al ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + TTYS0_TX_AL ; \ + ; \ + mov lword, %eax ; \ + shr $8, %eax ; \ + and $0x0f, %al ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + TTYS0_TX_AL ; \ + ; \ + mov lword, %eax ; \ + shr $4, %eax ; \ + and $0x0f, %al ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + TTYS0_TX_AL ; \ + ; \ + mov lword, %eax ; \ + and $0x0f, %al ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + TTYS0_TX_AL + + /* uses: esp, ebx, ax, dx */ #define TTYS0_TX_STRING(string) \ mov string, %ebx ; \ CALLSP(ttys0_tx_string) + /* uses: ebx, ax, dx */ +#define TTYS0_INLINE_TX_STRING(string) \ + movl string, %ebx ; \ +10: movb (%ebx), %al ; \ + incl %ebx ; \ + testb %al, %al ; \ + jz 11f ; \ + TTYS0_TX_AL ; \ + jmp 10b ; \ +11: + + /* uses: esp, ax, dx */ ttys0_tx_al: TTYS0_TX_AL diff --git a/src/rom/docmil_fill_inbuf.c b/src/rom/docmil_fill_inbuf.c index a32371460f..78b842074c 100644 --- a/src/rom/docmil_fill_inbuf.c +++ b/src/rom/docmil_fill_inbuf.c @@ -30,20 +30,20 @@ fill_inbuf(void) { if (firstfill) { if ((ram = malloc(K64)) == NULL) { - printk(KERN_EMERG "%6d:%s() - ram malloc failed\n", + printk_emerg("%6d:%s() - ram malloc failed\n", __LINE__, __FUNCTION__); return (0); } #ifdef CHECK_DOC_MIL if ((checkbuf = malloc(K64)) == NULL) { - printk(KERN_EMERG "%6d:%s() - checkbuf malloc failed\n", + printk_emerg("%6d:%s() - checkbuf malloc failed\n", __LINE__, __FUNCTION__); - printk(KERN_EMERG "Checking disabled\n"); + printk_emerg("Checking disabled\n"); } #endif - DBG("%6d:%s() - ram buffer:0x%p\n", + printk_debug("%6d:%s() - ram buffer:0x%p\n", __LINE__, __FUNCTION__, ram); block_count = 0; @@ -57,20 +57,20 @@ fill_inbuf(void) if (checkbuf) { memcpy_from_doc_mil(checkbuf, nvram, K64); if (memcmp(checkbuf, ram, K64)) { - printk("CHECKBUF FAILS for doc mil!\n"); - printk(KERN_EMERG "address 0x%x\n", nvram); + printk_emerg("CHECKBUF FAILS for doc mil!\n"); + printk_emerg( "address 0x%x\n", nvram); } } { int i; - printk(KERN_INFO "First 16 bytes of block: "); + printk_info( "First 16 bytes of block: "); for (i = 0; i < 16; i++) - printk("0x%x ", ram[i]); - printk(KERN_INFO "\n"); + printk_info("0x%x ", ram[i]); + printk_info( "\n"); } #endif - DBG("%6d:%s() - nvram:0x%p block_count:%d\n", + printk_debug("%6d:%s() - nvram:0x%p block_count:%d\n", __LINE__, __FUNCTION__, nvram, block_count); nvram += K64; diff --git a/src/rom/rom_fill_inbuf.c b/src/rom/rom_fill_inbuf.c index 52590fb1f2..dc61c1ace9 100644 --- a/src/rom/rom_fill_inbuf.c +++ b/src/rom/rom_fill_inbuf.c @@ -44,7 +44,7 @@ int fill_inbuf(void) } if (block_count > 31) { - printk(KERN_EMERG "%6d:%s() - overflowed source buffer\n", + printk_emerg( "%6d:%s() - overflowed source buffer\n", __LINE__, __FUNCTION__); inbuf = zkernel_start; inptr = 0; @@ -57,7 +57,7 @@ int fill_inbuf(void) #ifdef INBUF_COPY if (!ram) { - printk(KERN_EMERG "%6d:%s() - " + printk_emerg("%6d:%s() - " "ram malloc failed\n", __LINE__, __FUNCTION__); inbuf = zkernel_start; @@ -66,10 +66,10 @@ int fill_inbuf(void) return (0); } - DBG("%6d:%s() - ram buffer:0x%08x\n", + printk_debug("%6d:%s() - ram buffer:0x%08x\n", __LINE__, __FUNCTION__, ram); #endif - DBG("%6d:%s() - zkernel_start:0x%08x " + printk_debug("%6d:%s() - zkernel_start:0x%08x " "zkernel_mask:0x%08x\n", __LINE__, __FUNCTION__, zkernel_start, zkernel_mask); @@ -77,14 +77,14 @@ int fill_inbuf(void) nvram += K64; while (!(zkernel_mask & (1 << block_count))) { - DBG("%6d:%s() - skipping block %d\n", + printk_debug("%6d:%s() - skipping block %d\n", __LINE__, __FUNCTION__, block_count); block_count++; nvram += K64; if (block_count > 31) { - printk(KERN_EMERG "%6d:%s() - " + printk_emerg("%6d:%s() - " "overflowed source buffer\n", __LINE__, __FUNCTION__); inbuf = zkernel_start; @@ -98,7 +98,7 @@ int fill_inbuf(void) #ifdef INBUF_COPY memcpy(ram, nvram, K64); #endif - DBG("%6d:%s() - nvram:0x%p block_count:%d\n", + printk_debug("%6d:%s() - nvram:0x%p block_count:%d\n", __LINE__, __FUNCTION__, nvram, block_count); #ifdef INBUF_COPY diff --git a/src/rom/tsunami_tigbus_rom_fill_inbuf.c b/src/rom/tsunami_tigbus_rom_fill_inbuf.c index 8ac5af5e3a..23ca86534c 100644 --- a/src/rom/tsunami_tigbus_rom_fill_inbuf.c +++ b/src/rom/tsunami_tigbus_rom_fill_inbuf.c @@ -45,7 +45,7 @@ int fill_inbuf(void) firstfill = 0; ram = malloc(K64); if (!ram) { - printk(KERN_EMERG "%6d:%s() - " + printk_emerg("%6d:%s() - " "ram malloc failed\n", __LINE__, __FUNCTION__); return 0; @@ -53,30 +53,30 @@ int fill_inbuf(void) } if (block_count > 31) { - printk(KERN_EMERG "%6d:%s() - overflowed source buffer\n", + printk_emerg("%6d:%s() - overflowed source buffer\n", __LINE__, __FUNCTION__); insize = 0; return (0); } if (!block_count) { nvram = TIG_KERNEL_START; - DBG("%6d:%s() - ram buffer:0x%08x\n", + printk_debug("%6d:%s() - ram buffer:0x%08x\n", __LINE__, __FUNCTION__, ram); - DBG("%6d:%s() - TIG_KERNEL_START:0x%08x\n", + printk_debug("%6d:%s() - TIG_KERNEL_START:0x%08x\n", __LINE__, __FUNCTION__, TIG_KERNEL_START); } tsunami_flash_copy_from(ram, nvram, K64); - DBG("\n%6d:%s() - nvram:0x%lx block_count:%d\n", + printk_debug("\n%6d:%s() - nvram:0x%lx block_count:%d\n", __LINE__, __FUNCTION__, nvram, block_count); #if 0 { int i; for(i = 0; i < K64; i+= 16) { - printk("%05x: %02x %02x %02x %02x %02x %02x %02x %02x " + printk_debug("%05x: %02x %02x %02x %02x %02x %02x %02x %02x " "%02x %02x %02x %02x %02x %02x %02x %02x\n", (block_count << 16)+i, ram[i+0], ram[i+1], ram[i+2], ram[i+3], diff --git a/src/southbridge/acer/m1535/southbridge.c b/src/southbridge/acer/m1535/southbridge.c index 16704eda16..94c96c8cba 100644 --- a/src/southbridge/acer/m1535/southbridge.c +++ b/src/southbridge/acer/m1535/southbridge.c @@ -11,7 +11,7 @@ southbridge_fixup() pcidev = pci_find_device(PCI_VENDOR_ID_ACER, PCI_DEVICE_ID_ACER_M1535D, (void *)NULL); if (!pcidev) { - printk(KERN_ERR __FUNCTION__ "no southbridge for 0x%x:0x%x\n", + printk_err(__FUNCTION__ "no southbridge for 0x%x:0x%x\n", PCI_VENDOR_ID_ACER, PCI_DEVICE_ID_ACER_M1535D); return; } @@ -33,7 +33,7 @@ void nvram_on() pcidev = pci_find_device(PCI_VENDOR_ID_ACER, PCI_DEVICE_ID_ACER_M1535D, (void *)NULL); if (!pcidev) { - printk(KERN_ERR __FUNCTION__ "no southbridge for 0x%x:0x%x\n", + printk_err( __FUNCTION__ "no southbridge for 0x%x:0x%x\n", PCI_VENDOR_ID_ACER, PCI_DEVICE_ID_ACER_M1535D); return; } diff --git a/src/southbridge/intel/piix4e/southbridge.c b/src/southbridge/intel/piix4e/southbridge.c index 372774bd51..48e3a9e0c0 100644 --- a/src/southbridge/intel/piix4e/southbridge.c +++ b/src/southbridge/intel/piix4e/southbridge.c @@ -22,12 +22,12 @@ void nvram_on() struct pci_dev *pcidev; - printk(KERN_INFO "Enabling extended BIOS access..."); + printk_info( "Enabling extended BIOS access..."); pcidev = pci_find_device(0x8086, 0x7110, (void *)NULL); if (pcidev) pci_write_config_word(pcidev, 0x4e, 0x03c3); - printk(KERN_INFO "done.\n"); + printk_info("done.\n"); post_code(0x91); } @@ -52,13 +52,13 @@ void keyboard_on() pcidev = pci_find_device(0x8086, 0x7110, (void *)NULL); if (! pcidev) { - printk(KERN_ERR __FUNCTION__ "Can't find dev 0x7110\n"); + printk_err( __FUNCTION__ "Can't find dev 0x7110\n"); return; } /* oh no, we are setting this below. Fix it later. */ /* to do -- changed these to PciReadByte */ pci_read_config_byte(pcidev, 0x4e, ®val); - printk(KERN_DEBUG __FUNCTION__ "regcal at 0x4e is 0x%x\n", regval); + printk_debug( __FUNCTION__ "regcal at 0x4e is 0x%x\n", regval); regval |= 0x2; pci_write_config_byte(pcidev, 0x4e, regval); diff --git a/src/southbridge/via/vt8231/southbridge.c b/src/southbridge/via/vt8231/southbridge.c index 4150017c6d..c715aeeb66 100644 --- a/src/southbridge/via/vt8231/southbridge.c +++ b/src/southbridge/via/vt8231/southbridge.c @@ -65,18 +65,18 @@ void southbridge_fixup() // First do some more things to devfn (17,0) // note: this should already be cleared, according to the book. pcibios_read_config_byte(0, devfn, 0x50, &enables); - printk("IDE enable in reg. 50 is 0x%x\n", enables); + printk_debug("IDE enable in reg. 50 is 0x%x\n", enables); enables &= ~8; // need manifest constant here! - printk("set IDE reg. 50 to 0x%x\n", enables); + printk_debug("set IDE reg. 50 to 0x%x\n", enables); pcibios_write_config_byte(0, devfn, 0x50, enables); // set default interrupt values (IDE) pcibios_read_config_byte(0, devfn, 0x4c, &enables); - printk("IRQs in reg. 4c are 0x%x\n", enables & 0xf); + printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf); // clear out whatever was there. enables &= ~0xf; enables |= 4; - printk("setting reg. 4c to 0x%x\n", enables); + printk_debug("setting reg. 4c to 0x%x\n", enables); pcibios_write_config_byte(0, devfn, 0x4c, enables); // set up the serial port interrupts. @@ -85,30 +85,30 @@ void southbridge_fixup() pcibios_write_config_byte(0, devfn, 0x47, 0x03); devfn = PCI_DEVFN(17, 1); pcibios_read_config_byte(0, devfn, 0x40, &enables); - printk("enables in reg 0x40 0x%x\n", enables); + printk_debug("enables in reg 0x40 0x%x\n", enables); enables |= 3; pcibios_write_config_byte(0, devfn, 0x40, enables); pcibios_read_config_byte(0, devfn, 0x40, &enables); - printk("enables in reg 0x40 read back as 0x%x\n", enables); + printk_debug("enables in reg 0x40 read back as 0x%x\n", enables); // address decoding. // we want "flexible", i.e. 1f0-1f7 etc. or native PCI pcibios_read_config_byte(0, devfn, 0x9, &enables); - printk("enables in reg 0x9 0x%x\n", enables); + printk_debug("enables in reg 0x9 0x%x\n", enables); // by the book, set the low-order nibble to 0xa. enables &= ~0xf; // cf/cg silicon needs an 'f' here. enables |= 0xf; pcibios_write_config_byte(0, devfn, 0x9, enables); pcibios_read_config_byte(0, devfn, 0x9, &enables); - printk("enables in reg 0x9 read back as 0x%x\n", enables); + printk_debug("enables in reg 0x9 read back as 0x%x\n", enables); // standard bios sets master bit. pcibios_read_config_byte(0, devfn, 0x4, &enables); - printk("command in reg 0x4 0x%x\n", enables); + printk_debug("command in reg 0x4 0x%x\n", enables); enables |= 5; pcibios_write_config_byte(0, devfn, 0x4, enables); pcibios_read_config_byte(0, devfn, 0x4, &enables); - printk("command in reg 0x4 reads back as 0x%x\n", enables); + printk_debug("command in reg 0x4 reads back as 0x%x\n", enables); // oh well, the PCI BARs don't work right. // This chip will not work unless IDE runs at standard legacy diff --git a/src/southbridge/via/vt82c686/southbridge.c b/src/southbridge/via/vt82c686/southbridge.c index dc35153f6d..69b63482cc 100644 --- a/src/southbridge/via/vt82c686/southbridge.c +++ b/src/southbridge/via/vt82c686/southbridge.c @@ -65,18 +65,18 @@ void southbridge_fixup() // First do some more things to devfn (7,0) // note: this should already be cleared, according to the book. pcibios_read_config_byte(0, devfn, 0x48, &enables); - printk("IDE enable in reg. 48 is 0x%x\n", enables); + printk_debug("IDE enable in reg. 48 is 0x%x\n", enables); enables &= ~2; // need manifest constant here! - printk("set IDE reg. 48 to 0x%x\n", enables); + printk_debug("set IDE reg. 48 to 0x%x\n", enables); pcibios_write_config_byte(0, devfn, 0x48, enables); // set default interrupt values (IDE) pcibios_read_config_byte(0, devfn, 0x4a, &enables); - printk("IRQs in reg. 4a are 0x%x\n", enables & 0xf); + printk_debug("IRQs in reg. 4a are 0x%x\n", enables & 0xf); // clear out whatever was there. enables &= ~0xf; enables |= 4; - printk("setting reg. 4a to 0x%x\n", enables); + printk_debug("setting reg. 4a to 0x%x\n", enables); pcibios_write_config_byte(0, devfn, 0x4a, enables); // set up the serial port interrupts. @@ -85,30 +85,30 @@ void southbridge_fixup() devfn = PCI_DEVFN(7, 1); pcibios_read_config_byte(0, devfn, 0x40, &enables); - printk("enables in reg 0x40 0x%x\n", enables); + printk_debug("enables in reg 0x40 0x%x\n", enables); enables |= 3; pcibios_write_config_byte(0, devfn, 0x40, enables); pcibios_read_config_byte(0, devfn, 0x40, &enables); - printk("enables in reg 0x40 read back as 0x%x\n", enables); + printk_debug("enables in reg 0x40 read back as 0x%x\n", enables); // address decoding. // we want "flexible", i.e. 1f0-1f7 etc. or native PCI pcibios_read_config_byte(0, devfn, 0x9, &enables); - printk("enables in reg 0x9 0x%x\n", enables); + printk_debug("enables in reg 0x9 0x%x\n", enables); // by the book, set the low-order nibble to 0xa. enables &= ~0xf; // cf/cg silicon needs an 'f' here. enables |= 0xf; pcibios_write_config_byte(0, devfn, 0x9, enables); pcibios_read_config_byte(0, devfn, 0x9, &enables); - printk("enables in reg 0x9 read back as 0x%x\n", enables); + printk_debug("enables in reg 0x9 read back as 0x%x\n", enables); // standard bios sets master bit. pcibios_read_config_byte(0, devfn, 0x4, &enables); - printk("command in reg 0x4 0x%x\n", enables); + printk_debug("command in reg 0x4 0x%x\n", enables); enables |= 5; pcibios_write_config_byte(0, devfn, 0x4, enables); pcibios_read_config_byte(0, devfn, 0x4, &enables); - printk("command in reg 0x4 reads back as 0x%x\n", enables); + printk_debug("command in reg 0x4 reads back as 0x%x\n", enables); // oh well, the PCI BARs don't work right. // This chip will not work unless IDE runs at standard legacy diff --git a/src/superio/SMC/fdc37b807/superio.c b/src/superio/SMC/fdc37b807/superio.c index 891c9f270e..07ded70b98 100644 --- a/src/superio/SMC/fdc37b807/superio.c +++ b/src/superio/SMC/fdc37b807/superio.c @@ -168,7 +168,7 @@ finishup(struct superio *s) rv |= smc_configuration_state(addr, 0); return(rv); if (rv) - printk("For %s rv in finishup is %d\n", s->name, rv); + printk_info("For %s rv in finishup is %d\n", s->name, rv); } diff --git a/util/config/NLBConfig.py b/util/config/NLBConfig.py index edd1b1f541..6410c8278a 100644 --- a/util/config/NLBConfig.py +++ b/util/config/NLBConfig.py @@ -19,18 +19,13 @@ crt0base = ''; ldscriptbase = ''; makeoptions = {}; +makenooptions = {}; # rule format. Key is the rule name. value is a list of lists. The first # element of the list is the dependencies, the rest are actions. makebaserules = {}; treetop = ''; outputdir = ''; -# config variables for the ldscript -# Initialize the to zero so we get a link error if the -# are not set. -rambase = 0; -linuxbiosbase = 0; - objectrules = []; userrules = []; userdefines = []; @@ -225,10 +220,16 @@ def nsuperio(dir, superio_commands): # basically raminit can have a whole list of files. That's why # this is a list. def raminit(dir, file): - ramfilelist = command_vals['raminit'] + ramfilelist = command_vals['mainboardinit'] ramfilelist.append(file) print "Added ram init file: ", file +# A list of files for initializing a motherboard +def mainboardinit(dir, file): + mainboardfilelist = command_vals['mainboardinit'] + mainboardfilelist.append(file) + print "Added mainboard init file: ", file + def object(dir, obj_name): addobject_defaultrule(obj_name, dir) @@ -293,19 +294,37 @@ def adddepend(dir, rule): def makedefine(dir, rule): userdefines.append(rule) +def set_option(option, value): + if makenooptions.has_key(option): + del makenooptions[option] + makeoptions[option] = value + #print "option %s = %s\n" % (option, value) + +def clear_option(option): + if makeoptions.has_key(option): + del makeoptions[option] + makenooptions[option] = "" + #print "nooption %s \n" % (option) + def option(dir, option): - makeoptions[option] = "-D" + option + regexp = re.compile(r"^([^=]*)=(.*)$") + m = regexp.match(option) + key=option + value= "" + if m and m.group(1): + key = m.group(1) + value = m.group(2) + set_option(key, value) def nooption(dir, option): - makeoptions[option] = "-U" + option + clear_option(option) def commandline(dir, command): - makeoptions["CMD_LINE"] = "-DCMD_LINE=\'\"" + command + "\"\'" + set_option("CMD_LINE", "\"" + command + "\"") # we do all these rules by hand because docipl will always be special # it's more or less a stand-alone bootstrap def docipl(dir, ipl_name): - global rambase, linuxbiosbase mainboard = command_vals['mainboard'] mainboard_dir = os.path.join(treetop, 'src', mainboard) # add the docipl rule @@ -318,20 +337,18 @@ def docipl(dir, ipl_name): # Now we need a mainboard-specific include path userrules.append("\tcc $(CFLAGS) -I%s -c $<" % mainboard_dir) # now set new values for the ldscript.ld. Should be a script? - rambase = 0x4000 - linuxbiosbase = 0x80000 + set_option("_RAMBASE", 0x4000) + set_option("_ROMBASE", 0x80000) def linux(dir, linux_name): linuxrule = 'LINUX=' + linux_name makedefine(dir, linuxrule) def setrambase(dir, address): - global rambase - rambase = string.atol(address,0) + set_option("_RAMBASE", address) def setlinuxbiosbase(dir, address): - global linuxbiosbase - linuxbiosbase = string.atol(address,0) + set_option("_ROMBASE", address) list_vals = { # 'option': [] @@ -350,7 +367,8 @@ command_vals = { 'pcibridge' : [], # vendor, bridgename 'superio' : [], # vendor, superio name 'object' : {}, # path/filename.[cS] - 'raminit' : [], # set of files to include for ram init + 'mainboardinit' : [], # set of files to include for mainboard init + 'config_files' : [], # set of files we built the makefile from } command_actions = { @@ -368,6 +386,7 @@ command_actions = { 'object' : object, 'linux' : linux, 'raminit' : raminit, + 'mainboardinit' : mainboardinit, 'dir' : dir, 'keyboard' : keyboard, 'docipl' : docipl, @@ -397,8 +416,12 @@ def readfile(filename): def doconfigfile(dir, filename): if (debug): print "doconfigfile" , filename - filelines = readfile(filename) + config_file_list = command_vals['config_files'] + config_file_list.append(filename) if (debug): + print "doconfigfile: config_file_list ", config_file_list + filelines = readfile(filename) + if (debug > 1): print "doconfigfile: filelines", filelines # parse out command arguments /(.*)(#.*)/ for comments regexp = re.compile(r"([^#]*)(.*)") @@ -434,24 +457,25 @@ def doconfigfile(dir, filename): # write crt0 def writecrt0(path): crt0filepath = os.path.join(path, "crt0.S") - raminitfiles = command_vals["raminit"] - paramfile = os.path.join(treetop, 'src/include', - command_vals['northbridge'][0], "param.h") - paramfileinclude = '' + mainboardinitfiles = command_vals['mainboardinit'] + #paramfile = os.path.join(treetop, 'src/include', + # command_vals['northbridge'][0], "param.h") + #paramfileinclude = '' print "Trying to create ", crt0filepath # try: file = open(crt0filepath, 'w+') - print "Check for crt0.S param file:", paramfile - if os.path.isfile(paramfile): - ipfile = os.path.join(command_vals['northbridge'][0],"param.h") - paramfileinclude = "#include <%s>\n" % ipfile - print " Adding include to crt0.S for this parameter file:" - print " ", paramfileinclude + #print "Check for crt0.S param file:", paramfile + #if os.path.isfile(paramfile): + # ipfile = os.path.join(command_vals['northbridge'][0],"param.h") + # paramfileinclude = "#include <%s>\n" % ipfile + # print " Adding include to crt0.S for this parameter file:" + # print " ", paramfileinclude + # + ## serial for superio + #superioserial = "#include <%s/setup_serial.inc>\n" % command_vals['superio'] - # serial for superio - superioserial = "#include <%s/setup_serial.inc>\n" % command_vals['superio'] crt0lines = readfile(crt0base) if (debug): @@ -460,34 +484,35 @@ def writecrt0(path): if (string.strip(line) <> "CRT0_PARAMETERS"): file.write(line) else: - file.write(paramfileinclude) - # we will do this better at some point. - # possible we need a 'console' command. - file.write("\n"); - file.write("#ifdef SERIAL_CONSOLE\n"); - file.write(superioserial) - file.write("#include \n"); - file.write("TTYS0_TX_STRING($ttyS0_test)\n") - file.write("#endif /* SERIAL_CONSOLE */\n") - file.write("\n"); + #file.write(paramfileinclude) + ## we will do this better at some point. + ## possible we need a 'console' command. + #file.write("\n"); + #file.write("#ifdef SERIAL_CONSOLE\n"); + #file.write(superioserial) + #file.write("#include \n"); + #file.write("TTYS0_TX_STRING($ttyS0_test)\n") + #file.write("#endif /* SERIAL_CONSOLE */\n") + #file.write("\n"); - for i in range(len(raminitfiles)): - file.write("#include <%s>\n" % raminitfiles[i]) + for i in range(len(mainboardinitfiles)): + file.write("#include <%s>\n" % mainboardinitfiles[i]) file.close(); # write ldscript def writeldscript(path): - global rambase, linuxbiosbase ldfilepath = os.path.join(path, "ldscript.ld") print "Trying to create ", ldfilepath # try: file = open(ldfilepath, 'w+') - # print out the ldscript rules - # print out the values of defined variables - file.write('_ROMBASE = 0x%lx;\n' % linuxbiosbase) - file.write('_RAMBASE = 0x%lx;\n' % rambase) + keys = makeoptions.keys() + keys.sort() + for key in keys: + if makeoptions[key] : + file.write("%s = %s;\n" % (key, makeoptions[key])) + ldlines = readfile(ldscriptbase) if (debug): print "LDLINES ",ldlines @@ -495,8 +520,7 @@ def writeldscript(path): file.write(line) file.close(); - -# write ldscript +# write doxygen file def writedoxygenfile(path): global objectrules, doxyscriptbase doxyfilepath = os.path.join(path, "LinuxBIOSDoc.config") @@ -530,14 +554,30 @@ def writedoxygenfile(path): def writemakefile(path): makefilepath = os.path.join(path, "Makefile") + mainboardinitfiles = command_vals['mainboardinit'] + config_file_list = command_vals['config_files'] + print "Trying to create ", makefilepath + keys = makeoptions.keys() + keys.sort() # try: file = open(makefilepath, 'w+') file.write("TOP=%s\n" % (treetop)) + for key in keys: + if makeoptions[key] : + file.write("%s=%s\n" % (key, makeoptions[key])) + file.write("CPUFLAGS=\n") - for z in makeoptions.keys(): -# print "key is %s, val %s\n" % (z, makeoptions[z]) - file.write("CPUFLAGS += %s\n" % (makeoptions[z])) + for key in keys: +# print "key is %s, val %s\n" % (key, makeoptions[key]) +# file.write("CPUFLAGS += %s\n" % (makeoptions[key])) + if makeoptions[key] : + file.write("CPUFLAGS += -D%s=\'%s'\n" % (key, makeoptions[key])) + else: + file.write("CPUFLAGS += -D%s\n" % (key)) + + for key in makenooptions.keys(): + file.write("CPUFLAGS += -U%s\n" % (key)) # print out all the object dependencies # There is ALWAYS a crt0.o @@ -584,6 +624,16 @@ def writemakefile(path): # for i in range(len(linuxrules)): # file.write("%s\n" % linuxrules[i]) + # print out the dependencies for crt0.s + for i in range(len(mainboardinitfiles)): + file.write("crt0.s: $(TOP)/src/%s\n" % mainboardinitfiles[i]) + + # print out the dependencies for Makefile + file.write("Makefile crt0.S ldscript.ld nsuperio.c: %s/%s $(TOP)/util/config/NLBConfig.py $(TOP)/src/arch/$(ARCH)/config/make.base $(TOP)/src/arch/$(ARCH)/config/ldscript.base $(TOP)/src/arch/$(ARCH)/config/crt0.base \n\tpython $(TOP)/util/config/NLBConfig.py %s/%s $(TOP)\n" + % (config_path, config_file, config_path, config_file)) + for i in range(len(config_file_list)): + file.write("Makefile: %s\n" % config_file_list[i]) + file.close(); # except IOError: # print "File open and write failed for ", makefilepath