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Code changes from my work and the AMD760MP chipset.

Browse source 
The primary changes is the way in which printk works.
But there are many other assorted code cleanups.
Just look and see :)
This commit is contained in:
Eric W. Biederman 2001-08-08 02:45:10 +00:00
commit ed8c9d7e0d
62 changed files with 1362 additions and 977 deletions
Download patch file Download diff file Expand all files Collapse all files

10
src/arch/alpha/lib/hardwaremain.c
View file

@ -9,10 +9,10 @@ void hardwaremain(unsigned long signature, unsigned long memsize,
early_mainboard_init();
displayinit();
printk("\n\nsignature=0x%016lx memsize=0x%016lx cpu_speed=0x%016lx\n",
printk_info("\n\nsignature=0x%016lx memsize=0x%016lx cpu_speed=0x%016lx\n",
signature, memsize, cpu_speed);
elfboot(memsize >> 10 /* In kilobytes */);
printk("\n after elfboot\n");
printk_err("\n after elfboot\n");
}
void fatal_error(unsigned long exception_handler, unsigned long exception_at,
@ -21,9 +21,9 @@ void fatal_error(unsigned long exception_handler, unsigned long exception_at,
/* Just in case we are totally messed up */
early_mainboard_init();
displayinit();
printk("\n\nFault: 0x%0lx\n", exception_handler);
printk("PC: 0x%0lx\n", exception_at);
printk("RA: 0x%0lx\n", return_address);
printk_emerg("\n\nFault: 0x%0lx\n", exception_handler);
printk_emerg("PC: 0x%0lx\n", exception_at);
printk_emerg("RA: 0x%0lx\n", return_address);
/* Now spin forever */
while(1) {;}
}

1
src/arch/i386/lib/Config
View file

@ -1,3 +1,4 @@
object i386_subr.o
object params.o
object hardwaremain.o
object pirq_routing.o

247
src/arch/i386/lib/hardwaremain.c
View file

@ -32,57 +32,122 @@ it with the version available from LANL.
static char rcsid[] = "$Id$";
#endif
#include <cpu/p5/io.h>
#include <intel.h>
#include <arch/io.h>
#include <arch/intel.h>
#include <pciconf.h>
#include <pci.h>
#include <cpu/p5/cpuid.h>
#include <cpu/p6/ioapic.h>
#include <subr.h>
#include <printk.h>
void intel_main()
{
// These are only used here, so don't bother putting them in a .h
void mainboard_fixup(void);
void nvram_on(void);
void keyboard_on(void);
void framebuffer_on(void);
void intel_copy_irq_routing_table(void);
unsigned long sizeram(void);
void intel_cache_on(unsigned long base, unsigned long totalram);
void intel_zero_irq_settings(void);
void intel_check_irq_routing_table(void);
void intel_interrupts_on();
#ifdef FINAL_MAINBOARD_FIXUP
void final_mainboard_fixup(void);
#endif /* FINAL_MAINBOARD_FIXUP */
#ifdef USE_NEW_SUPERIO_INTERFACE
extern struct superio *all_superio;
extern int nsuperio;
extern void handle_superio(int pass, struct superio *s, int nsuperio);
#include <smp/start_stop.h>
#include <cpu/l2_cache.h>
#include <cpu/cpufixup.h>
#include <cpu/p5/cpuid.h>
#include <part/mainboard.h>
#include <part/keyboard.h>
#include <part/framebuffer.h>
#include <part/nvram.h>
#include <part/floppy.h>
#include <part/sizeram.h>
#include <part/hard_reset.h>
#include <arch/ioapic.h>
#include <pc80/i8259.h>
#include <pc80/keyboard.h>
#include <arch/i386_subr.h>
#include <arch/pirq_routing.h>
#include <arch/ioapic.h>
#include <smp/atomic.h>
#if defined(SMP)
#include<arch/smp/mpspec.h>
#include<arch/smp/atomic.h>
#endif
#ifdef CONFIGURE_L2_CACHE
int intel_l2_configure();
#endif /* CONFIGURE_L2_CACHE */
#ifdef CPU_FIXUP
// some cpus need a fixup done. This is the hook for doing that
// For now we call it after pci config and sizing.
// we may move it earlier for speed.
static int cpu_initialize(unsigned long totalram)
{
/* Because we busy wait at the printk spinlock.
* It is important to keep the number of printed messages
* from secondary cpus to a minimum, when debugging is
* disabled.
*/
int processor_id = this_processors_id();
printk_notice("Initializing CPU #%d\n", processor_id);
/* some cpus need a fixup done. This is the hook for doing that. */
cpufixup(totalram);
/* Turn on caching if we haven't already */
cache_on(totalram);
display_cpuid();
mtrr_check();
/* now that everything is really up, enable the l2 cache if desired.
* The enable can wait until this point, because linuxbios and it's
* data areas are tiny, easily fitting into the L1 cache.
*/
configure_l2_cache();
interrupts_on();
printk_info("CPU #%d Initialized\n", processor_id);
return processor_id;
}
static unsigned long get_ramsize(void)
{
unsigned long totalram;
totalram = sizeram();
// can't size just yet ...
// mainboard totalram sizing may not be up yet. If it is not ready,
// take a default of 64M
if (!totalram)
totalram = 64 * 1024;
return totalram;
}
#ifdef SMP
/* Number of cpus that are currently running in linuxbios */
static atomic_t active_cpus = ATOMIC_INIT(1);
void secondary_cpu_init(void)
{
unsigned long totalram;
int processor_id;
atomic_inc(&active_cpus);
totalram = get_ramsize();
processor_id = cpu_initialize(totalram);
atomic_dec(&active_cpus);
stop_cpu(processor_id);
}
static void wait_for_other_cpus(void)
{
int old_active_count, active_count;
old_active_count = 1;
active_count = atomic_read(&active_cpus);
while(active_count > 1) {
if (active_count != old_active_count) {
printk_info("Waiting for %d CPUS to stop\n", active_count);
old_active_count = active_count;
}
active_count = atomic_read(&active_cpus);
}
}
#else /* SMP */
#define wait_for_other_cpus() do {} while(0)
#endif /* SMP */
void hardwaremain(int boot_complete)
{
// Comment: the NEW_SUPERIO architecture is actually pretty good.
// I think we need to move to the same sort of architecture for
// everything: A config file generated sequence of calls
// for initializing all the chips. We stick with this
// for now -- rgm.
void cpufixup(unsigned long totalram);
#ifdef USE_NEW_SUPERIO_INTERFACE
extern struct superio *all_superio;
extern int nsuperio;
extern void handle_superio(int pass, struct superio *s, int nsuperio);
#endif
#ifdef UPDATE_MICROCODE
void intel_display_cpuid_microcode(void);
#endif /* UPDATE_MICROCODE */
/* the order here is a bit tricky. We don't want to do much of
* anything that uses config registers until after PciAllocateResources
* since that function also figures out what kind of config strategy
@ -99,138 +164,102 @@ void intel_main()
post_code(0x39);
printk(KERN_INFO "Reached intel_main().\n");
printk_notice("LinuxBIOS %s...\n", (boot_complete)?"rebooting":"booting");
post_code(0x40);
#ifdef UPDATE_MICROCODE
post_code(0x41);
printk(KERN_INFO "Updating microcode\n");
intel_display_cpuid_microcode();
#endif /* UPDATE_MICROCODE */
post_code(0x42);
/* If we have already booted attempt a hard reboot */
if (boot_complete) {
hard_reset();
}
// pick how to scan the bus. This is first so we can get at memory size.
printk(KERN_INFO "Finding PCI confiuration type...\n");
printk_info("Finding PCI configuration type.\n");
pci_set_method();
post_code(0x5f);
#ifdef USE_NEW_SUPERIO_INTERFACE
handle_superio(0, all_superio, nsuperio);
#endif
printk(KERN_INFO "Scanning PCI bus...");
pci_enumerate();
post_code(0x66);
printk(KERN_INFO "done\n");
// The framebuffer can change how much memory you have.
// So you really need to run this before you size ram.
#ifdef HAVE_FRAMEBUFFER
framebuffer_on();
#endif /* HAVE_FRAMEBUFFER */
totalram = sizeram();
totalram = get_ramsize();
post_code(0x70);
printk(KERN_INFO "totalram: %ldM\n", totalram/1024);
printk_info("totalram: %ldM\n", totalram/1024);
// can't size just yet ...
// mainboard totalram sizing may not be up yet. If it is not ready,
// take a default of 64M
if (!totalram)
totalram = 64 * 1024;
/* Fully initialize the cpu before configuring the bus */
cpu_initialize(totalram);
#ifdef CPU_FIXUP
// cpu-dependent fixup.
cpufixup(totalram);
#endif
// Turn on cache before configuring the bus.
printk(KERN_INFO "Enabling cache...");
intel_cache_on(0, totalram);
post_code(0x80);
printk(KERN_INFO "done.\n");
/* Now start the other cpus initializing
* The sooner they start the sooner they stop.
*/
startup_other_cpus();
printk(KERN_INFO "Allocating PCI resources...");
// Now do the real bus
// we round the total ram up a lot for thing like the SISFB, which
// shares high memory with the CPU.
pci_configure();
post_code(0x88);
pci_enable();
post_code(0x90);
printk(KERN_INFO "done.\n");
#ifdef IOAPIC
/* set up the IO-APIC for the clock interrupt. */
post_code(0x92);
setup_ioapic();
#endif /* IOAPIC */
// generic mainboard fixup
mainboard_fixup();
#ifndef MAINBOARD_FIXUP_IN_CHARGE
post_code(0x91);
setup_i8259();
/* set up the IO-APIC for the clock interrupt. */
post_code(0x92);
setup_ioapic();
nvram_on();
intel_display_cpuid();
intel_mtrr_check();
#ifndef NO_KEYBOARD
keyboard_on();
#endif /* NO_KEYBOARD */
#ifndef USE_NEW_SUPERIO_INTERFACE
#ifdef MUST_ENABLE_FLOPPY
enable_floppy();
post_code(0x95);
#endif /* MUST_ENABLE_FLOPPY */
#endif
#ifdef USE_NEW_SUPERIO_INTERFACE
handle_superio(1, all_superio, nsuperio);
#endif
#ifdef SMP
/* copy the smp block to address 0 */
intel_smpblock((void *)16);
post_code(0x96);
#endif /* SMP */
pci_zero_irq_settings();
intel_zero_irq_settings();
intel_check_irq_routing_table();
intel_copy_irq_routing_table();
/* copy the smp block to address 0 */
write_smp_table((void *)16);
post_code(0x96);
check_pirq_routing_table();
copy_pirq_routing_table();
post_code(0x9a);
/* to do: intel_serial_on(); */
intel_interrupts_on();
#ifdef FINAL_MAINBOARD_FIXUP
printk(KERN_INFO "Final mainboard fixup for ");
post_code(0xec);
final_mainboard_fixup();
printk(KERN_INFO "done.\n");
#endif /* FINAL_MAINBOARD_FIXUP */
post_code(0xec);
#ifdef CONFIGURE_L2_CACHE
/* now that everything is really up, enable the l2 cache if desired.
* The enable can wait until this point, because linuxbios and it's
* data areas are tiny, easily fitting into the L1 cache.
*/
printk(KERN_INFO "Configuring L2 cache...");
intel_l2_configure();
printk(KERN_INFO "done.\n");
#endif /* CONFIGURE_L2_CACHE */
#endif /* MAINBOARD_FIXUP_IN_CHARGE */
#ifdef USE_NEW_SUPERIO_INTERFACE
handle_superio(2, all_superio, nsuperio);
#endif
/* make certain we are the only cpu running in linuxBIOS */
wait_for_other_cpus();
#ifdef LINUXBIOS
printk(KERN_INFO "Jumping to linuxbiosmain()...\n");
printk_info("Jumping to linuxbiosmain()...\n");
// we could go to argc, argv, for main but it seems like overkill.
post_code(0xed);
linuxbiosmain(0, totalram);

176
src/arch/i386/lib/i386_subr.c
View file

@ -1,16 +1,19 @@
#include <cpu/p5/io.h>
#include <cpu/p5/macros.h>
#include <cpu/p6/msr.h>
#include <cpu/p6/apic.h>
#include <cpu/p6/mtrr.h>
#include <printk.h>
#include <pci.h>
#include <subr.h>
#include <string.h>
#include <i386_subr.h>
#include <arch/i386_subr.h>
void intel_cache_on(unsigned long base, unsigned long totalram)
void cache_on(unsigned long totalram)
{
post_code(0x60);
printk_info("Enabling cache...");
/* we need an #ifdef i586 here at some point ... */
__asm__ __volatile__("mov %cr0, %eax\n\t"
@ -22,15 +25,17 @@ void intel_cache_on(unsigned long base, unsigned long totalram)
* so absolute minimum needed to get it going.
*/
/* OK, linux it turns out does nothing. We have to do it ... */
#ifdef i686
#if defined(i686)
// totalram here is in linux sizing, i.e. units of KB.
// set_mtrr is responsible for getting it into the right units!
intel_set_mtrr(base, totalram);
setup_mtrrs(totalram);
#endif
post_code(0x6A);
printk_info("done.\n");
}
void intel_interrupts_on()
void interrupts_on()
{
/* this is so interrupts work. This is very limited scope --
* linux will do better later, we hope ...
@ -39,128 +44,57 @@ void intel_interrupts_on()
* stuff. So we have to do things differently ...
* see the Intel mp1.4 spec, page A-3
*/
#ifdef SMP
unsigned long reg, *regp;
#define SVR 0xfee000f0
#define LVT1 0xfee00350
#define LVT2 0xfee00360
#define APIC_ENABLED 0x100
printk(KERN_INFO "Enabling interrupts...");
regp = (unsigned long *) SVR;
reg = *regp;
reg &= (~0xf0);
reg |= APIC_ENABLED;
*regp = reg;
regp = (unsigned long *) LVT1;
reg = *regp;
reg &= 0xfffe00ff;
reg |= 0x5700;
*regp = reg;
regp = (unsigned long *) LVT2;
reg = *regp;
reg &= 0xfffe00ff;
reg |= 0x5400;
*regp = reg;
#else /* !SMP */
#ifdef i686
/* Only Pentium Pro and later have thos MSR stuff */
#if defined(SMP)
/* Only Pentium Pro and later have those MSR stuff */
unsigned long low, high;
printk(KERN_INFO "Enabling interrupts...");
printk_info("Setting up local apic...");
rdmsr(0x1b, low, high);
low &= ~0x800;
wrmsr(0x1b, low, high);
/* Enable the local apic */
rdmsr(APIC_BASE_MSR, low, high);
low |= APIC_BASE_MSR_ENABLE;
low &= ~APIC_BASE_MSR_ADDR_MASK;
low |= APIC_DEFAULT_BASE;
wrmsr(APIC_BASE_MSR, low, high);
/* Put the local apic in virtual wire mode */
apic_write_around(APIC_SPIV,
(apic_read_around(APIC_SPIV) & ~(APIC_VECTOR_MASK))
| APIC_SPIV_ENABLE);
apic_write_around(APIC_LVT0,
(apic_read_around(APIC_LVT0) &
~(APIC_LVT_MASKED | APIC_LVT_LEVEL_TRIGGER |
APIC_LVT_REMOTE_IRR | APIC_INPUT_POLARITY |
APIC_SEND_PENDING |APIC_LVT_RESERVED_1 |
APIC_DELIVERY_MODE_MASK))
| (APIC_LVT_REMOTE_IRR |APIC_SEND_PENDING |
APIC_DELIVERY_MODE_EXTINT)
);
apic_write_around(APIC_LVT1,
(apic_read_around(APIC_LVT1) &
~(APIC_LVT_MASKED | APIC_LVT_LEVEL_TRIGGER |
APIC_LVT_REMOTE_IRR | APIC_INPUT_POLARITY |
APIC_SEND_PENDING |APIC_LVT_RESERVED_1 |
APIC_DELIVERY_MODE_MASK))
| (APIC_LVT_REMOTE_IRR |APIC_SEND_PENDING |
APIC_DELIVERY_MODE_NMI)
);
#else /* SMP */
#ifdef i686
/* Only Pentium Pro and later have those MSR stuff */
unsigned long low, high;
printk_info("Disabling local apic...");
rdmsr(APIC_BASE_MSR, low, high);
low &= ~APIC_BASE_MSR_ENABLE;
wrmsr(APIC_BASE_MSR, low, high);
#endif /* i686 */
#endif /* SMP */
printk(KERN_INFO "done.\n");
printk_info("done.\n");
post_code(0x9b);
}
/* These functions should be chip-set independent -tds */
void intel_zero_irq_settings(void)
{
struct pci_dev *pcidev;
unsigned char line;
printk(KERN_INFO "Zeroing IRQ settings...");
pcidev = pci_devices;
while (pcidev) {
pci_read_config_byte(pcidev, 0x3d, &line);
if (line) {
pci_write_config_byte(pcidev, 0x3c, 0);
}
pcidev = pcidev->next;
}
printk(KERN_INFO "done.\n");
}
void intel_check_irq_routing_table(void)
{
#ifdef HAVE_PIRQ_TABLE
const u8 *addr;
const struct irq_routing_table *rt;
int i;
u8 sum;
printk(KERN_INFO "Checking IRQ routing tables...");
rt = &intel_irq_routing_table;
addr = (u8 *)rt;
sum = 0;
for (i = 0; i < rt->size; i++)
sum += addr[i];
DBG("%s:%6d:%s() - irq_routing_table located at: 0x%p\n",
__FILE__, __LINE__, __FUNCTION__, addr);
sum = (unsigned char)(rt->checksum-sum);
if (sum != rt->checksum) {
printk(KERN_WARNING "%s:%6d:%s() - "
"checksum is: 0x%02x but should be: 0x%02x\n",
__FILE__, __LINE__, __FUNCTION__, rt->checksum, sum);
}
if (rt->signature != PIRQ_SIGNATURE || rt->version != PIRQ_VERSION ||
rt->size % 16 || rt->size < sizeof(struct irq_routing_table)) {
printk(KERN_WARNING "%s:%6d:%s() - "
"Interrupt Routing Table not valid\n",
__FILE__, __LINE__, __FUNCTION__);
return;
}
sum = 0;
for (i=0; i<rt->size; i++)
sum += addr[i];
if (sum) {
printk(KERN_WARNING "%s:%6d:%s() - "
"checksum error in irq routing table\n",
__FILE__, __LINE__, __FUNCTION__);
}
printk(KERN_INFO "done.\n");
#endif /* #ifdef HAVE_PIRQ_TABLE */
}
#define RTABLE_DEST 0xf0000
void intel_copy_irq_routing_table(void)
{
#ifdef HAVE_PIRQ_TABLE
printk(KERN_INFO "Copying IRQ routing tables...");
memcpy((char *) RTABLE_DEST, &intel_irq_routing_table, intel_irq_routing_table.size);
printk(KERN_INFO "done.\n");
#endif
}